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path: root/arch/arm64/include/asm/cache.h
Commit message (Expand)AuthorAgeFilesLines
* arm64: Kill detection of VPIPT i-cache policyMarc Zyngier2023-12-051-6/+0
* arm64: allow kmalloc() caches aligned to the smaller cache_line_size()Catalin Marinas2023-06-191-0/+3
* KVM: arm64: Normalize cache configurationAkihiko Odaki2023-01-211-0/+3
* arm64/cache: Move CLIDR macro definitionsAkihiko Odaki2023-01-121-0/+6
* arm64: cache: Remove unused CTR_CACHE_MINLINE_MASKKristina Martsenko2022-09-091-4/+0
* arm64/cache: Fix cache_type_cwg() for register generationMark Brown2022-08-231-1/+1
* arm64/sysreg: Standardise naming for CTR_EL0 fieldsMark Brown2022-07-051-22/+9
* arm64/cache: Restrict which headers are included in __ASSEMBLY__Mark Brown2022-07-051-6/+5
* arm64/cpuinfo: Remove references to reserved cache typeMark Brown2022-07-051-1/+0
* mm: make minimum slab alignment a runtime propertyPeter Collingbourne2022-05-131-5/+12
* Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)"Will Deacon2021-07-121-1/+1
* arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)Will Deacon2021-06-011-1/+1
* arm64: kasan: simplify and inline MTE functionsAndrey Konovalov2021-02-261-1/+0
* arm64: kasan: align allocations for HW_TAGSAndrey Konovalov2020-12-221-0/+3
* arm64: avoid -Woverride-init warningArnd Bergmann2020-10-281-0/+1
* treewide: Convert macro and uses of __section(foo) to __section("foo")Joe Perches2020-10-251-1/+1
* arm64: Ask the compiler to __always_inline functions used by KVM at HYPJames Morse2020-02-221-1/+1
* arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419James Morse2019-10-251-1/+2
* arm64: prefer __section from compiler_attributes.hNick Desaulniers2019-08-131-1/+1
* Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2019-07-081-1/+4
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| * arm64/mm: Correct the cache line size warning with non coherent deviceMasayoshi Mizuma2019-06-171-0/+7
| * arm64: cacheinfo: Update cache_line_size detected from DT or PPTTShaokun Zhang2019-06-041-5/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-191-12/+1
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* kasan, arm64: remove redundant ARCH_SLAB_MINALIGN defineAndrey Konovalov2019-01-161-2/+0
* kasan, arm64: use ARCH_SLAB_MINALIGN instead of manual aligningAndrey Konovalov2019-01-081-0/+6
* arm64: cpufeature: Fix handling of CTR_EL0.IDC fieldSuzuki K Poulose2018-10-161-0/+40
* arm64: Fix mismatched cache line size detectionSuzuki K Poulose2018-07-051-0/+4
* arm64: Increase ARCH_DMA_MINALIGN to 128Catalin Marinas2018-05-151-2/+2
* Revert "arm64: Increase the max granular size"Catalin Marinas2018-05-111-1/+1
* Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"Will Deacon2018-03-271-3/+3
* arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDCShanker Donthineni2018-03-091-0/+4
* arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)Catalin Marinas2018-03-061-3/+3
* arm64: cache: Identify VPIPT I-cachesWill Deacon2017-03-201-0/+7
* arm64: cache: Merge cachetype.h into cache.hWill Deacon2017-03-201-1/+30
* arm64: Increase the max granular sizeTirumalesh Chalamarla2015-10-281-1/+1
* arm64: Implement support for read-mostly sectionsJungseok Lee2014-12-031-0/+2
* arm64: Implement cache_line_size() based on CTR_EL0.CWGCatalin Marinas2014-05-091-1/+12
* arm64: Cache maintenance routinesCatalin Marinas2012-09-171-0/+32
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