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path: root/arch/arm64/kernel/cpufeature.c
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* Merge branch 'for-next/mte' into for-next/coreWill Deacon2020-10-021-0/+35
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| * arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTECatalin Marinas2020-09-041-0/+18
| * arm64: mte: CPU feature detection and initial sysreg configurationVincenzo Frascino2020-09-031-0/+17
* | Merge branch 'for-next/ghostbusters' into for-next/coreWill Deacon2020-10-021-48/+3
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| * | arm64: Rewrite Spectre-v4 mitigation codeWill Deacon2020-09-291-41/+0
| * | arm64: Treat SSBS as a non-strict system featureWill Deacon2020-09-291-3/+3
| * | arm64: Remove Spectre-related CONFIG_* optionsWill Deacon2020-09-291-4/+0
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*---. \ Merge branches 'for-next/acpi', 'for-next/boot', 'for-next/bpf', 'for-next/cp...Will Deacon2020-10-021-9/+37
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| | | * arm64: cpufeature: Export symbol read_sanitised_ftr_reg()Jean-Philippe Brucker2020-09-281-0/+1
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| | * arm64: cpufeature: Modify address authentication cpufeature to exactAmit Daniel Kachhap2020-09-141-9/+35
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| * arm64: dbm: Invalidate local TLB when setting TCR_EL1.HDWill Deacon2020-10-011-0/+1
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* treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva2020-08-231-1/+1
* Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2020-08-031-43/+106
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| * Merge branch 'for-next/tlbi' into for-next/coreCatalin Marinas2020-07-311-0/+20
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| | * arm64: tlb: Detect the ARMv8.4 TLBI RANGE featureZhenyu Ye2020-07-151-0/+10
| | * arm64: Detect the ARMv8.4 TTL featureMarc Zyngier2020-07-071-0/+11
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| *-. \ Merge branches 'for-next/misc', 'for-next/vmcoreinfo', 'for-next/cpufeature',...Catalin Marinas2020-07-311-29/+85
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| | | * arm64/cpufeature: Validate feature bits spacing in arm64_ftr_regs[]Anshuman Khandual2020-07-071-3/+44
| | | * arm64/cpufeature: Replace all open bits shift encodings with macrosAnshuman Khandual2020-07-031-26/+27
| | | * arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 registerAnshuman Khandual2020-07-031-0/+7
| | | * arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 registerAnshuman Khandual2020-07-031-0/+4
| | | * arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 registerAnshuman Khandual2020-07-031-0/+3
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| * / arm64/panic: Unify all three existing notifier blocksAnshuman Khandual2020-07-021-14/+1
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* / arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718Sai Prakash Ranjan2020-07-031-0/+2
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* arm64: kpti: Add KRYO{3, 4}XX silver CPU cores to kpti safelistSai Prakash Ranjan2020-06-241-0/+2
* Merge branch 'for-next/bti' into for-next/coreWill Deacon2020-05-281-0/+37
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| * arm64: Set GP bit in kernel page tables to enable BTI for the kernelMark Brown2020-05-071-0/+4
| * Merge branch 'for-next/bti-user' into for-next/btiWill Deacon2020-05-051-0/+33
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| | * arm64: Basic Branch Target Identification supportDave Martin2020-03-161-0/+33
* | | KVM: arm64: Check advertised Stage-2 page size capabilityMarc Zyngier2020-05-281-0/+18
* | | arm64/cpufeature: Add get_arm64_ftr_reg_nowarn()Anshuman Khandual2020-05-271-10/+34
* | | arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 contextAnshuman Khandual2020-05-211-0/+4
* | | arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 registerAnshuman Khandual2020-05-211-0/+2
* | | arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 registerAnshuman Khandual2020-05-211-0/+2
* | | arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 registerAnshuman Khandual2020-05-211-0/+1
* | | arm64/cpufeature: Add remaining feature bits in ID_MMFR4 registerAnshuman Khandual2020-05-211-0/+13
* | | arm64/cpufeature: Add remaining feature bits in ID_PFR0 registerAnshuman Khandual2020-05-211-0/+2
* | | arm64/cpufeature: Introduce ID_MMFR5 CPU registerAnshuman Khandual2020-05-211-0/+10
* | | arm64/cpufeature: Introduce ID_DFR1 CPU registerAnshuman Khandual2020-05-211-0/+10
* | | arm64/cpufeature: Introduce ID_PFR2 CPU registerAnshuman Khandual2020-05-211-0/+11
* | | arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0Anshuman Khandual2020-05-211-1/+1
* | | arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 registerAnshuman Khandual2020-05-211-1/+1
* | | arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 registerAnshuman Khandual2020-05-211-2/+12
* | | arm64/cpufeature: Drop open encodings while extracting parangeAnshuman Khandual2020-05-201-1/+2
* | | arm64/cpufeature: Validate hypervisor capabilities during CPU hotplugAnshuman Khandual2020-05-201-0/+32
* | | arm64: cpufeature: Extend comment to describe absence of field infoWill Deacon2020-05-051-0/+5
* | | arm64: cpufeature: Add an overview comment for the cpufeature frameworkWill Deacon2020-04-281-0/+50
* | | arm64: cpufeature: Relax checks for AArch32 support at EL[0-2]Will Deacon2020-04-281-7/+3
* | | arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit onlyWill Deacon2020-04-281-1/+32
* | | arm64: cpufeature: Factor out checking of AArch32 featuresWill Deacon2020-04-281-47/+65
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