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path: root/arch/mips/include/asm/mipsregs.h
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* MIPS: set mips32r5 for virt extensionsNick Desaulniers2021-06-291-4/+4
* MIPS: Make check condition for SDBBP consistent with EJTAG specTiezhu Yang2021-02-111-0/+4
* MIPS: Loongson-3: Enable COP2 usage in kernelHuacai Chen2020-09-211-0/+7
* MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer2020-09-071-2/+2
* MIPS: Remove PNX833x alias NXP_STB22xThomas Bogendoerfer2020-08-241-12/+0
* MIPS: handle Loongson-specific GSExc exceptionWANG Xuerui2020-07-311-0/+3
* MIPS: add definitions for Loongson-specific CP0.Diag1 registerWANG Xuerui2020-07-311-0/+8
* MIPS: Unify naming style of vendor CP0.Config6 bitsHuacai Chen2020-07-081-14/+14
* KVM: MIPS: Add CONFIG6 and DIAG registers emulationHuacai Chen2020-06-041-0/+4
* MIPS: Tidy up CP0.Config6 bits definitionHuacai Chen2020-05-241-13/+24
* mips: Add CONFIG/CONFIG6/Cause reg fields macroSerge Semin2020-05-221-0/+19
* mips: Add CP0 Write Merge config supportSerge Semin2020-05-221-0/+3
* mips: MAAR: Use more precise address maskSerge Semin2020-05-211-1/+1
* mips: MAAR: Add XPA mode supportSerge Semin2020-05-191-0/+10
* MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bitsWANG Xuerui2020-05-171-0/+6
* MIPS: Add MAC2008 SupportJiaxun Yang2020-01-221-0/+3
* MIPS: Ingenic: Disable abandoned HPTLB function.Zhou Yanjie2019-11-221-0/+6
* MIPS: Ingenic: Disable broken BTB lookup optimization.Zhou Yanjie2019-08-051-0/+4
* MIPS: MemoryMapID (MMID) SupportPaul Burton2019-02-041-0/+4
* MIPS: Add GINVT instruction helpersPaul Burton2019-02-041-0/+7
* MIPS: Avoid using .set mips0 to restore ISAPaul Burton2018-11-091-10/+20
* MIPS: Cleanup DSP ASE detectionPaul Burton2018-10-161-1/+19
* Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/l...Linus Torvalds2018-08-131-10/+19
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| * MIPS: Use dins to simplify __write_64bit_c0_split()Paul Burton2018-08-071-1/+10
| * MIPS: Use read-write output operand in __write_64bit_c0_split()Paul Burton2018-08-071-9/+7
| * MIPS: Loongson64: Define and use some CP0 registersHuacai Chen2018-07-231-0/+2
* | Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"Rafał Miłecki2018-07-271-3/+0
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* MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratumTokunori Ikegami2018-06-181-0/+3
* MIPS: Probe for MIPS MT perf counters per TCMatt Redfearn2018-05-151-0/+5
* MIPS: Add crc instruction support flag to elf_hwcapMarcin Nowakowski2018-02-191-0/+1
* MIPS: XPA: Standardise readx/writex accessorsJames Hogan2018-01-221-10/+10
* MIPS: XPA: Allow use of $0 (zero) to MTHC0James Hogan2018-01-221-2/+2
* MIPS: XPA: Use XPA instructions in assemblyJames Hogan2018-01-221-10/+16
* MIPS: VZ: Pass GC0 register names in $n formatJames Hogan2018-01-221-188/+188
* MIPS: VZ: Update helpers to use new asm macrosJames Hogan2018-01-221-127/+37
* MIPS: Add helpers for assembler macro instructionsJames Hogan2018-01-221-0/+83
* MIPS: mipsregs.h: Make read_c0_prid use const accessorJames Hogan2018-01-091-1/+1
* MIPS: mipsregs.h: Add read const Cop0 macrosJames Hogan2018-01-091-10/+27
* MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split'Maciej W. Rozycki2017-11-081-8/+6
* MIPS: Fix input modify in __write_64bit_c0_split()James Hogan2017-09-211-6/+9
* MIPS: Add accessor & bit definitions for GlobalNumberPaul Burton2017-08-301-0/+13
* MIPS: MIPS16e2: Identify ASE presenceMaciej W. Rozycki2017-07-051-0/+1
* KVM: MIPS/VZ: Handle Octeon III guest.PRid registerJames Hogan2017-03-281-0/+2
* MIPS: Add Octeon III register accessors & definitionsJames Hogan2017-03-281-0/+36
* MIPS: Add some missing guest CP0 accessors & defsJames Hogan2017-03-281-2/+14
* MIPS: Separate MAAR V bit into VL and VH for XPAJames Hogan2017-03-281-1/+7
* MIPS: Unify perf counter register definitionsJames Hogan2017-02-141-0/+33
* MIPS: Mask out limit field when calculating wired entry countPaul Burton2016-11-241-0/+6
* MIPS: Stop setting I6400 FTLBPPaul Burton2016-09-291-2/+0
* MIPS: Add define for Config.VI (virtual icache) bitJames Hogan2016-06-151-0/+1
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