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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-02-21105-1123/+6390
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| * MIPS: sead3: Corrected get_c0_perfcount_intNiklas Cassel2015-02-201-1/+1
| * MIPS: mm: Remove dead macro definitionsAndreas Ruprecht2015-02-202-16/+0
| * MIPS: OCTEON: irq: add CIB and other fixesDavid Daney2015-02-201-269/+780
| * MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.David Daney2015-02-201-2/+43
| * MIPS: OCTEON: More OCTEONIII supportChandrakala Chavva2015-02-204-2/+326
| * MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.Chad Reese2015-02-201-20/+0
| * MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.David Daney2015-02-202-6/+17
| * MIPS: OCTEON: Update octeon-model.h code for new SoCs.David Daney2015-02-205-27/+90
| * MIPS: OCTEON: Implement DCache errata workaround for all CN6XXXDavid Daney2015-02-203-4/+8
| * MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.hDavid Daney2015-02-201-30/+105
| * MIPS: OCTEON: Implement the core-16057 workaroundDavid Daney2015-02-201-0/+22
| * MIPS: OCTEON: Delete unused COP2 saving codeAleksey Makarov2015-02-201-26/+0
| * MIPS: OCTEON: Use correct instruction to read 64-bit COP0 registerChandrakala Chavva2015-02-201-3/+3
| * MIPS: OCTEON: Save and restore CP2 SHA3 stateDavid Daney2015-02-203-11/+35
| * MIPS: OCTEON: Fix FP context save.David Daney2015-02-201-12/+7
| * MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUsDavid Daney2015-02-204-32/+150
| * MIPS: boot: Provide more uImage optionsMarkos Chandras2015-02-202-2/+55
| * MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.hDavid Daney2015-02-201-6/+0
| * MIPS: ip22-gio: Remove legacy suspend/resume supportLars-Peter Clausen2015-02-202-26/+0
| * mips: pci: Add ifdef around pci_proc_domainZubair Lutfullah Kakakhel2015-02-201-0/+2
| * MIPS: Alchemy: Fix cpu clock calculationManuel Lauss2015-02-201-0/+2
| * MIPS: Alchemy: remove declaration for set_cpuspecManuel Lauss2015-02-201-1/+0
| * MIPS: Alchemy: preset loops_per_jiffy based on CPU clockManuel Lauss2015-02-202-0/+9
| * MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculationManuel Lauss2015-02-201-5/+14
| * MIPS: Add set/clear CP0 macros for PageGrain registerSteven J. Hill2015-02-203-4/+5
| * MIPS: Usage and cosmetic cleanups of page table bits.Steven J. Hill2015-02-192-62/+38
| * Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/...Ralf Baechle2015-02-1965-415/+4405
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| | * MIPS: Add Malta QEMU 32R6 defconfigMarkos Chandras2015-02-171-0/+193
| | * MIPS: Malta: Add support for building MIPS R6 kernelMarkos Chandras2015-02-171-0/+2
| | * MIPS: kernel: elf: Improve the overall ABI and FPU mode checksMarkos Chandras2015-02-173-132/+194
| | * MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6Markos Chandras2015-02-171-1/+2
| | * MIPS: kernel: process: Do not allow FR=0 on MIPS R6Markos Chandras2015-02-171-0/+4
| | * MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras2015-02-172-5/+6
| | * MIPS: Make use of the ERETNC instruction on MIPS R6Markos Chandras2015-02-175-4/+28
| | * MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6Leonid Yegoshin2015-02-178-5/+2518
| | * MIPS: asm: mipsregs: Add support for the LLADDR registerMarkos Chandras2015-02-171-0/+2
| | * MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras2015-02-174-0/+7
| | * MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras2015-02-173-1/+20
| | * MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras2015-02-173-1/+16
| | * MIPS: Emulate the new MIPS R6 BALC instructionMarkos Chandras2015-02-173-1/+19
| | * MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructionsMarkos Chandras2015-02-173-2/+7
| | * MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructionsMarkos Chandras2015-02-173-1/+21
| | * MIPS: Emulate the new MIPS R6 branch compact (BC) instructionMarkos Chandras2015-02-173-1/+23
| | * MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructionsMarkos Chandras2015-02-172-0/+47
| | * MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructionsMarkos Chandras2015-02-172-0/+55
| | * MIPS: Emulate the BC1{EQ,NE}Z FPU instructionsMarkos Chandras2015-02-173-30/+101
| | * MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6Markos Chandras2015-02-172-13/+89
| | * MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6Markos Chandras2015-02-173-2/+15
| | * MIPS: mm: scache: Add secondary cache support for MIPS R6 coresMarkos Chandras2015-02-172-2/+4
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