Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | riscv: add memory-type errata for T-Head | Heiko Stuebner | 2022-05-11 | 1 | -0/+21 |
* | riscv: integrate alternatives better into the main architecture | Heiko Stuebner | 2022-05-11 | 1 | -11/+2 |
* | riscv: alternative only works on !XIP_KERNEL | Jisheng Zhang | 2022-03-10 | 1 | -0/+1 |
* | riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y | Vincent Chen | 2021-05-06 | 1 | -2/+2 |
* | riscv: sifive: Apply errata "cip-1200" patch | Vincent Chen | 2021-04-26 | 1 | -0/+11 |
* | riscv: sifive: Apply errata "cip-453" patch | Vincent Chen | 2021-04-26 | 1 | -0/+11 |
* | riscv: sifive: Add SiFive alternative ports | Vincent Chen | 2021-04-26 | 1 | -0/+10 |
* | riscv: Introduce alternative mechanism to apply errata solution | Vincent Chen | 2021-04-26 | 1 | -0/+12 |