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* riscv: errata: thead: use pa based instructions for CMOJisheng Zhang2024-01-101-12/+6
* riscv: errata: thead: use riscv_nonstd_cache_ops for CMOJisheng Zhang2024-01-101-2/+73
* RISC-V: alternative: Remove feature_probe_funcEvan Green2023-09-011-8/+0
* riscv: errata: thead: only set cbom size & noncoherent during bootJisheng Zhang2023-07-061-2/+5
* RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap2023-04-291-3/+3
* RISC-V: hwprobe: Remove __init on probe_vendor_features()Evan Green2023-04-251-3/+3
* Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt2023-04-181-0/+10
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| * RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-181-0/+10
* | riscv: alternatives: Rename errata_id to patch_idAndrew Jones2023-03-141-2/+2
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* RISC-V: take text_mutex during alternative patchingConor Dooley2023-02-211-2/+6
* riscv: Fix early alternative patchingSamuel Holland2023-02-141-3/+1
* riscv: switch to relative alternative entriesJisheng Zhang2023-01-311-3/+8
* drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx coresHeiko Stuebner2022-10-271-0/+19
* Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt2022-10-131-6/+8
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| * riscv: check for kernel config option in t-head memory types errataHeiko Stuebner2022-10-131-0/+3
| * riscv: use BIT() macros in t-head errata initHeiko Stuebner2022-10-131-2/+2
| * riscv: drop some idefs from CMO initializationHeiko Stuebner2022-10-131-4/+3
* | RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt2022-09-131-0/+1
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* riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner2022-08-031-0/+20
* riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner2022-06-161-26/+12
* riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-112-0/+93
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