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* RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt2022-09-131-0/+1
* riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt2022-08-101-0/+20
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| * riscv: implement cache-management errata for T-Head SoCsHeiko Stuebner2022-08-031-0/+20
* | Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-08-061-26/+12
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| * riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner2022-06-161-26/+12
* | riscv: don't warn for sifive erratas in modulesHeiko Stuebner2022-07-071-1/+2
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* riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-114-1/+100
* riscv: implement module alternativesHeiko Stuebner2022-05-111-5/+9
* riscv: allow different stages with alternativesHeiko Stuebner2022-05-111-1/+2
* riscv: integrate alternatives better into the main architectureHeiko Stuebner2022-05-112-76/+0
* riscv: errata: alternative: mark vendor_patch_func __initdataJisheng Zhang2022-01-091-1/+2
* riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent2021-06-011-1/+1
* riscv: sifive: Apply errata "cip-1200" patchVincent Chen2021-04-261-0/+18
* riscv: sifive: Apply errata "cip-453" patchVincent Chen2021-04-263-0/+59
* riscv: sifive: Add SiFive alternative portsVincent Chen2021-04-264-0/+75
* riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2021-04-262-0/+70
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