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path: root/arch/riscv/include/asm/cpufeature.h
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* Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt2024-01-171-0/+2
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| * riscv: Add static key for misaligned accessesCharlie Jenkins2024-01-171-0/+2
* | riscv: add ISA extension parsing for scalar cryptoEvan Green2023-12-121-1/+3
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* riscv: Rearrange hwcap.h and cpufeature.hXiao Wang2023-11-091-0/+83
* RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-071-1/+0
* Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-051-0/+18
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| * riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-011-0/+18
* | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-211-0/+1
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* RISC-V: Probe for unaligned access speedEvan Green2023-09-011-0/+2
* RISC-V: Track ISA extensions per hartEvan Green2023-06-191-0/+10
* RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-181-0/+2
* RISC-V: Move struct riscv_cpuinfo to new headerEvan Green2023-04-181-0/+21