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path: root/arch/riscv/include/asm/sbi.h
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* RISC-V: Add SBI HSM extension definitionsAtish Patra2020-03-311-0/+14
* RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-0/+2
* RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-0/+14
* RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-0/+2
* RISC-V: Add SBI v0.2 extension definitionsAtish Patra2020-03-311-0/+21
* RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-311-71/+68
* RISC-V: Mark existing SBI as 0.1 SBI.Atish Patra2020-03-311-19/+22
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-171-0/+2
* riscv: add support for MMIO access to the timer registersChristoph Hellwig2019-11-131-1/+2
* riscv: implement remote sfence.i using IPIsChristoph Hellwig2019-11-131-0/+3
* riscv: poison SBI calls for M-modeChristoph Hellwig2019-11-131-2/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* riscv: fix sbi_remote_sfence_vma{,_asid}.Gary Guo2019-05-161-7/+12
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-261-0/+100
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