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path: root/arch/riscv/include/asm/smp.h
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* riscv: Switch to hotplug core state synchronizationThomas Gleixner2023-05-151-1/+1
* RISC-V: Allow marking IPIs as suitable for remote FENCEsAnup Patel2023-04-081-2/+16
* RISC-V: Treat IPIs as normal Linux IRQsAnup Patel2023-04-081-14/+21
* riscv: kexec: Fixup crash_smp_send_stop without multi coresGuo Ren2022-11-291-0/+3
* riscv: smp: Add 64bit hartid support on RV64Sunil V L2022-07-191-2/+2
* RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra2022-01-201-2/+0
* RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=nSean Christopherson2022-01-091-8/+2
* riscv: remove cpu_stop()Jisheng Zhang2022-01-091-2/+0
* riscv: Constify sbi_ipi_opsJisheng Zhang2021-04-261-2/+2
* RISC-V: Add mechanism to provide custom IPI operationsAnup Patel2020-08-201-0/+19
* RISC-V: Fix build warning for smpboot.cAtish Patra2020-08-041-0/+3
* RISC-V: self-contained IPI handling routineAnup Patel2020-06-091-0/+3
* RISC-V: Support cpu hotplugAtish Patra2020-03-311-0/+17
* RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-0/+7
* riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-051-6/+0
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Move cpuid to hartid mapping to SMP.Atish Patra2019-03-041-5/+13
* RISC-V: Show IPI statsAnup Patel2018-10-221-0/+9
* RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-221-1/+23
* RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-221-10/+4
* clocksource: new RISC-V SBI timer driverPalmer Dabbelt2018-08-131-3/+0
* RISC-V: simplify software interrupt / IPI codeChristoph Hellwig2018-08-131-3/+0
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+52
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