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* riscv: uaccess: fix type of 0 variable on error in get_user()Ben Dooks2023-01-181-1/+1
* RISC-V: fix barrier() use in <vdso/processor.h>Randy Dunlap2022-06-251-0/+2
* arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where neededArnd Bergmann2021-11-061-0/+2
* riscv: Workaround mcount name prior to clang-13Nathan Chancellor2021-05-221-2/+12
* riscv: virt_addr_valid must check the address belongs to linear mappingAlexandre Ghiti2021-02-231-1/+4
* RISC-V: Take text_mutex in ftrace_init_nop()Palmer Dabbelt2020-10-011-0/+7
* RISC-V: Upgrade smp_mb__after_spinlock() to iorw,iorwPalmer Dabbelt2020-07-291-1/+9
* riscv: use 16KB kernel stack on 64-bitAndreas Schwab2020-07-221-0/+4
* riscv/atomic: Fix sign extension for RV64INathan Huckleberry2020-06-301-4/+4
* riscv: Make __fstate_clean() work correctly.Vincent Chen2019-08-251-1/+1
* riscv: fix accessing 8-byte variable from RV32Alan Kao2019-05-081-1/+1
* riscv: Fix syscall_get_arguments() and syscall_set_arguments()Dmitry V. Levin2019-04-171-5/+7
* riscv: Adjust mmap base address at a third of task sizeAlexandre Ghiti2019-03-131-1/+1
* riscv: Add pte bit to distinguish swap from invalidStefan O'Rear2019-02-202-4/+10
* riscv: fix warning in arch/riscv/include/asm/module.hDavid Abdurachmanov2018-12-131-0/+1
* RISC-V: Fix raw_copy_{to,from}_user()Olof Johansson2018-11-271-2/+2
* RISC-V: include linux/ftrace.h in asm-prototypes.hJames Cowgill2018-09-241-0/+7
* riscv: tlb: Provide definition of tlb_flush() before including tlb.hWill Deacon2018-08-281-0/+4
* RISC-V: Fix sys_riscv_flush_icachePalmer Dabbelt2018-08-202-2/+5
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| * RISC-V: Don't use a global include guard for uapi/asm/syscalls.hPalmer Dabbelt2018-08-201-0/+5
| * RISC-V: Define sys_riscv_flush_icache when SMP=nPalmer Dabbelt2018-08-201-2/+0
* | riscv: Delete asm/compat.hDeepa Dinamani2018-08-202-29/+1
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* Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-08-194-10/+3
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| * RISC-V: Fix !CONFIG_SMP compilation errorAtish Patra2018-08-131-0/+1
| * clocksource: new RISC-V SBI timer driverPalmer Dabbelt2018-08-131-3/+0
| * RISC-V: add a definition for the SIE SEIE bitChristoph Hellwig2018-08-131-0/+1
| * RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.hChristoph Hellwig2018-08-131-4/+0
| * RISC-V: simplify software interrupt / IPI codeChristoph Hellwig2018-08-132-3/+1
* | locking/atomics: Rework ordering barriersMark Rutland2018-07-251-12/+5
* | atomics/treewide: Make unconditional inc/dec ops optionalMark Rutland2018-06-211-76/+0
* | atomics/treewide: Make test ops optionalMark Rutland2018-06-211-46/+0
* | atomics/riscv: Define atomic64_fetch_add_unless()Mark Rutland2018-06-211-6/+2
* | atomics/treewide: Make atomic_fetch_add_unless() optionalMark Rutland2018-06-211-0/+1
* | atomics/treewide: Make atomic64_inc_not_zero() optionalMark Rutland2018-06-211-7/+0
* | atomics/treewide: Remove redundant atomic_inc_not_zero() definitionsMark Rutland2018-06-211-9/+0
* | atomics/treewide: Rename __atomic_add_unless() => atomic_fetch_add_unless()Mark Rutland2018-06-211-2/+2
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* Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2018-06-165-5/+92
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| * RISC-V: Make our port sparse-cleanPalmer Dabbelt2018-06-113-5/+7
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| | * riscv: split the declaration of __copy_userLuc Van Oostenryck2018-06-091-3/+5
| | * riscv: use NULL instead of a plain 0Luc Van Oostenryck2018-06-072-2/+2
| * | perf: riscv: preliminary RISC-V supportAlan Kao2018-06-042-0/+85
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* | mm: introduce ARCH_HAS_PTE_SPECIALLaurent Dufour2018-06-071-3/+0
* | riscv: add swiotlb supportChristoph Hellwig2018-05-191-0/+15
* | PCI: remove PCI_DMA_BUS_IS_PHYSChristoph Hellwig2018-05-071-3/+0
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* riscv: there is no <asm/handle_irq.h>Christoph Hellwig2018-04-241-1/+0
* Merge tag 'riscv-for-linus-4.17-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-04-047-234/+799
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| * RISC-V: Fixes to module loadingPalmer Dabbelt2018-04-021-0/+113
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| | * RISC-V: Add section of GOT.PLT for kernel moduleZong Li2018-04-021-15/+25
| | * RISC-V: Add sections of PLT and GOT for kernel moduleZong Li2018-04-021-0/+103
| * | RISC-V: Assorted memory model fixesPalmer Dabbelt2018-04-025-234/+630
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