summaryrefslogtreecommitdiffstats
path: root/arch/riscv/include
Commit message (Expand)AuthorAgeFilesLines
* riscv: add asm/unistd.h UAPI headerDavid Abdurachmanov2018-11-202-10/+21
* riscv: fix warning in arch/riscv/include/asm/module.hDavid Abdurachmanov2018-11-201-0/+1
* RISC-V: Fix raw_copy_{to,from}_user()Olof Johansson2018-11-201-2/+2
* riscv: fix spacing in struct pt_regsDavid Abdurachmanov2018-11-121-2/+2
* Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-311-3/+0
|\
| * Move EM_RISCV into elf-em.hPalmer Dabbelt2018-10-311-3/+0
* | treewide: remove current_text_addrNick Desaulniers2018-10-311-6/+0
* | Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-257-17/+192
|\|
| * RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-223-15/+50
| |\
| | * RISC-V: Show IPI statsAnup Patel2018-10-221-0/+9
| | * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-3/+13
| | * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-221-1/+23
| | * RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-221-1/+1
| | * RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-221-10/+4
| * | riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-221-1/+11
| |\ \
| | * | Auto-detect whether a FPU existsAlan Kao2018-10-221-4/+4
| | * | Allow to disable FPU supportAlan Kao2018-10-221-0/+10
| | |/
| * | RISC-V: Add futex support.Jim Wilson2018-10-222-1/+128
| * | RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-221-0/+3
| |/
* | Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-251-0/+1
|\ \
| * | RISC-V: Request newstat syscallsGuenter Roeck2018-09-051-0/+1
* | | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2018-10-242-24/+1
|\ \ \ | |_|/ |/| |
| * | signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZEEric W. Biederman2018-10-032-24/+1
| |/
* | RISC-V: include linux/ftrace.h in asm-prototypes.hJames Cowgill2018-09-241-0/+7
* | riscv: tlb: Provide definition of tlb_flush() before including tlb.hWill Deacon2018-08-281-0/+4
|/
* RISC-V: Fix sys_riscv_flush_icachePalmer Dabbelt2018-08-203-7/+13
|\
| * RISC-V: Don't use a global include guard for uapi/asm/syscalls.hPalmer Dabbelt2018-08-202-5/+13
| * RISC-V: Define sys_riscv_flush_icache when SMP=nPalmer Dabbelt2018-08-201-2/+0
* | riscv: Delete asm/compat.hDeepa Dinamani2018-08-202-29/+1
|/
* Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-08-194-10/+3
|\
| * RISC-V: Fix !CONFIG_SMP compilation errorAtish Patra2018-08-131-0/+1
| * clocksource: new RISC-V SBI timer driverPalmer Dabbelt2018-08-131-3/+0
| * RISC-V: add a definition for the SIE SEIE bitChristoph Hellwig2018-08-131-0/+1
| * RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.hChristoph Hellwig2018-08-131-4/+0
| * RISC-V: simplify software interrupt / IPI codeChristoph Hellwig2018-08-132-3/+1
* | locking/atomics: Rework ordering barriersMark Rutland2018-07-251-12/+5
* | Merge tag 'v4.18-rc5' into locking/core, to pick up fixesIngo Molnar2018-07-171-2/+7
|\|
| * RISC-V: Add definiion of extract symbol's index and type for 32-bitZong Li2018-07-041-2/+7
* | atomics/treewide: Make unconditional inc/dec ops optionalMark Rutland2018-06-211-76/+0
* | atomics/treewide: Make test ops optionalMark Rutland2018-06-211-46/+0
* | atomics/riscv: Define atomic64_fetch_add_unless()Mark Rutland2018-06-211-6/+2
* | atomics/treewide: Make atomic_fetch_add_unless() optionalMark Rutland2018-06-211-0/+1
* | atomics/treewide: Make atomic64_inc_not_zero() optionalMark Rutland2018-06-211-7/+0
* | atomics/treewide: Remove redundant atomic_inc_not_zero() definitionsMark Rutland2018-06-211-9/+0
* | atomics/treewide: Rename __atomic_add_unless() => atomic_fetch_add_unless()Mark Rutland2018-06-211-2/+2
|/
* Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2018-06-165-5/+92
|\
| * RISC-V: Make our port sparse-cleanPalmer Dabbelt2018-06-113-5/+7
| |\
| | * riscv: split the declaration of __copy_userLuc Van Oostenryck2018-06-091-3/+5
| | * riscv: use NULL instead of a plain 0Luc Van Oostenryck2018-06-072-2/+2
| * | perf: riscv: preliminary RISC-V supportAlan Kao2018-06-042-0/+85
| |/
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-07 07:48:45 +0000