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* Merge tag 'riscv-for-linus-5.8-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-06-119-15/+148
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| * riscv: use vDSO common flow to reduce the latency of the time-related functionsVincent Chen2020-06-107-10/+144
| * clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel2020-06-091-2/+0
| * irqchip: RISC-V per-HART local interrupt controller driverAnup Patel2020-06-091-2/+0
| * RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-091-0/+1
| * RISC-V: self-contained IPI handling routineAnup Patel2020-06-092-1/+3
* | mm: consolidate pte_index() and pte_offset_*() definitionsMike Rapoport2020-06-092-27/+0
* | mm: reorder includes after introduction of linux/pgtable.hMike Rapoport2020-06-093-4/+2
* | mm: introduce include/linux/pgtable.hMike Rapoport2020-06-094-5/+3
* | mm: rename flush_icache_user_range to flush_icache_user_pageChristoph Hellwig2020-06-081-1/+2
* | riscv: use asm-generic/cacheflush.hChristoph Hellwig2020-06-081-59/+3
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* Merge tag 'riscv-for-linus-5.8-mw0' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-06-047-2/+516
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| * riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structureYash Shah2020-05-201-0/+15
| * riscv: Remove the 'riscv_' prefix of function nameZong Li2020-05-181-2/+2
| * riscv: Add SW single-step support for KDBVincent Chen2020-05-181-0/+219
| * riscv: Use the XML target descriptions to report 3 system registersVincent Chen2020-05-182-1/+124
| * riscv: Add KGDB supportVincent Chen2020-05-182-0/+118
| * riscv: Allow device trees to be built into the kernelPalmer Dabbelt2020-05-181-0/+39
* | riscv: support DEBUG_WXZong Li2020-06-031-0/+11
* | mm/hugetlb: define a generic fallback for arch_clear_hugepage_flags()Anshuman Khandual2020-06-031-4/+0
* | mm/hugetlb: define a generic fallback for is_hugepage_only_range()Anshuman Khandual2020-06-031-6/+0
* | mm: switch the test_vmalloc module to use __vmalloc_nodeChristoph Hellwig2020-06-021-2/+2
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* riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'Kefeng Wang2020-05-131-0/+1
* riscv: pgtable: Fix __kernel_map_pages build error if NOMMUKefeng Wang2020-05-131-0/+2
* riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMUKefeng Wang2020-05-122-0/+3
* riscv: perf: RISCV_BASE_PMU should be independentKefeng Wang2020-05-121-6/+2
* RISC-V: Remove unused code from STRICT_KERNEL_RWXAtish Patra2020-05-051-8/+0
* RISC-V: Remove N-extension related definesAnup Patel2020-05-041-3/+0
* RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel2020-05-041-0/+22
* arch: split MODULE_ARCH_VERMAGIC definitions out to <asm/vermagic.h>Masahiro Yamada2020-04-232-2/+9
* mm/vma: define a default value for VM_DATA_DEFAULT_FLAGSAnshuman Khandual2020-04-101-2/+1
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-0913-75/+313
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| * riscv: Add SOC early init supportDamien Le Moal2020-04-031-0/+23
| * RISC-V: Support cpu hotplugAtish Patra2020-03-312-0/+29
| * RISC-V: Add SBI HSM extension definitionsAtish Patra2020-03-311-0/+14
| * RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-0/+2
| * RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-311-0/+34
| * RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-312-0/+21
| * RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-0/+2
| * RISC-V: Add SBI v0.2 extension definitionsAtish Patra2020-03-311-0/+21
| * RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-311-71/+68
| * RISC-V: Mark existing SBI as 0.1 SBI.Atish Patra2020-03-311-19/+22
| * riscv: Use macro definition instead of magic numberZong Li2020-03-261-1/+1
| * riscv: Add support to dump the kernel page tablesZong Li2020-03-262-0/+21
| * riscv: introduce interfaces to patch kernel codeZong Li2020-03-262-0/+14
| * riscv: add macro to get instruction lengthZong Li2020-03-261-0/+8
| * riscv: add STRICT_KERNEL_RWX supportZong Li2020-03-261-0/+8
| * riscv: add alignment for text, rodata and data sectionsZong Li2020-03-261-0/+13
| * riscv: add ARCH_HAS_SET_DIRECT_MAP supportZong Li2020-03-261-0/+3
| * riscv: add ARCH_HAS_SET_MEMORY supportZong Li2020-03-261-0/+24
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