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path: root/arch/riscv/kernel/alternative.c
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* riscv: errata: Rename defines for AndesYu Chien Peter Lin2024-03-121-1/+1
* Merge patch series "Add non-coherent DMA support for AX45MP"Palmer Dabbelt2023-09-081-0/+5
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| * riscv: errata: Add Andes alternative portsLad Prabhakar2023-09-011-0/+5
* | RISC-V: alternative: Remove feature_probe_funcEvan Green2023-09-011-19/+0
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* RISC-V: hwprobe: Remove __init on probe_vendor_features()Evan Green2023-04-251-2/+2
* RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-181-0/+19
* riscv: alternative: proceed one more instruction for auipc/jalr pairJisheng Zhang2023-02-211-0/+1
* riscv: alternative: patch alternatives in the vDSOJisheng Zhang2023-01-311-0/+29
* riscv: fix jal offsets in patched alternativesJisheng Zhang2023-01-241-0/+27
* RISC-V: fix auipc-jalr addresses in patched alternativesHeiko Stuebner2022-12-291-0/+56
* riscv: make patch-function pointer more generic in cpu_manufacturer_info structHeiko Stuebner2022-06-161-9/+9
* riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-111-0/+26
* riscv: don't use global static vars to store alternative dataHeiko Stuebner2022-05-111-27/+24
* riscv: add RISC-V Svpbmt extension supportHeiko Stuebner2022-05-111-0/+2
* riscv: implement module alternativesHeiko Stuebner2022-05-111-4/+14
* riscv: allow different stages with alternativesHeiko Stuebner2022-05-111-9/+17
* riscv: integrate alternatives better into the main architectureHeiko Stuebner2022-05-111-0/+75
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