summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel/cpu.c
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley2023-06-211-3/+5
* RISC-V: split early & late of_node to hartid mappingConor Dooley2023-06-211-1/+21
* Merge patch series "riscv: allow case-insensitive ISA string parsing"Palmer Dabbelt2023-06-061-1/+2
|\
| * riscv: allow case-insensitive ISA string parsingYangyu Chen2023-06-061-1/+2
* | RISC-V: cpu: Enable cpuinfo for ACPI systemsSunil V L2023-06-011-8/+22
|/
* Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini2023-05-051-0/+2
|\
| * RISC-V: Detect AIA CSRs from ISA stringAnup Patel2023-04-211-0/+2
* | Merge patch series "RISC-V Hardware Probing User Interface"Palmer Dabbelt2023-04-181-6/+2
|\ \
| * | RISC-V: Move struct riscv_cpuinfo to new headerEvan Green2023-04-181-6/+2
| |/
* | Merge patch series "RISC-V: Apply Zicboz to clear_page"Palmer Dabbelt2023-03-151-0/+1
|\ \
| * | RISC-V: Add Zicboz detection and block size parsingAndrew Jones2023-03-141-0/+1
| |/
* | Merge patch series "riscv, mm: detect svnapot cpu support at runtime"Palmer Dabbelt2023-03-091-0/+1
|\ \ | |/ |/|
| * riscv: mm: modify pte format for SvnapotQinglin Pan2023-03-071-0/+1
* | RISC-V: fix ordering of Zbb extensionHeiko Stuebner2023-02-211-1/+1
|/
* RISC-V: add zbb support to string functionsHeiko Stuebner2023-01-311-0/+1
* Merge patch series "Putting some basic order on isa extension lists"Palmer Dabbelt2023-01-191-15/+38
|\
| * RISC-V: resort all extensions in consistent ordersConor Dooley2023-01-171-2/+2
| * RISC-V: clarify ISA string ordering rules in cpu.cConor Dooley2023-01-171-13/+36
* | Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-12-141-3/+27
|\ \
| * | RISC-V: Cache SBI vendor valuesHeiko Stuebner2022-10-271-3/+27
| |/
* / RISC-V: Fix /proc/cpuinfo cpumask warningAndrew Jones2022-10-271-0/+3
|/
* Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-10-141-0/+51
|\
| * RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputPalmer Dabbelt2022-10-131-0/+51
| |\
| | * RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputAnup Patel2022-10-031-0/+51
* | | Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2022-10-111-0/+1
|\ \ \ | |/ / |/| |
| * | RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale2022-10-021-0/+1
| |/
* / RISC-V: Print SSTC in canonical orderPalmer Dabbelt2022-10-061-1/+1
|/
* RISC-V: Add Sstc extension supportPalmer Dabbelt2022-08-111-0/+1
|\
| * RISC-V: Enable sstc extension parsing from DTAtish Patra2022-08-111-0/+1
* | arch/riscv: add Zihintpause supportDao Lu2022-08-111-0/+1
* | riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt2022-08-101-0/+1
|\ \
| * | riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner2022-07-281-0/+1
| |/
* / riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-191-11/+15
|/
* riscv: Don't output a bogus mmu-type on a no MMU kernelNiklas Cassel2022-05-211-0/+4
* riscv: add RISC-V Svpbmt extension supportHeiko Stuebner2022-05-111-0/+1
* riscv: cpu.c: don't use kernel-doc markers for commentsRandy Dunlap2022-03-311-2/+2
* RISC-V: Fix a comment typo in riscv_of_parent_hartid()Atish Patra2022-03-301-1/+1
* perf: RISC-V: Add support for SBI PMU and SscofpmfPalmer Dabbelt2022-03-211-0/+1
|\
| * RISC-V: Add sscofpmf extension supportAtish Patra2022-03-211-0/+1
* | RISC-V: Provide a fraemework for RISC-V ISA extensionsPalmer Dabbelt2022-03-171-2/+63
|\|
| * RISC-V: Improve /proc/cpuinfo output for ISA extensionsAtish Patra2022-03-171-2/+63
* | riscv: mm: Set sv57 on defaultlyQinglin Pan2022-02-141-1/+3
|/
* riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfoAlexandre Ghiti2022-01-191-11/+12
* riscv: Use of_get_cpu_hwid()Rob Herring2021-10-201-1/+2
* RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-091-0/+16
* RISC-V: Remove unsupported isa string info printAtish Patra2019-10-281-42/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra2019-04-301-2/+1
* RISC-V: Remove NR_CPUs check during hartid search from DTAtish Patra2019-03-041-4/+0
* riscv: treat cpu devicetree nodes without status as enabledJohan Hovold2019-02-111-7/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-15 23:57:35 +0000