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path: root/arch/riscv/kernel/setup.c
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* RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel2019-03-261-8/+0
* RISC-V: Fixmap support and MM cleanupsPalmer Dabbelt2019-03-041-126/+4
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| * RISC-V: Move setup_vm() to mm/init.cAnup Patel2019-02-211-49/+0
| * RISC-V: Move setup_bootmem() to mm/init.cAnup Patel2019-02-211-72/+0
| * RISC-V: Setup init_mm before parse_early_param()Anup Patel2019-02-211-5/+4
* | arch: riscv: fix logic error in parse_dtbAndreas Schwab2019-03-041-1/+1
* | RISC-V: Move cpuid to hartid mapping to SMP.Atish Patra2019-03-041-9/+0
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* riscv: use pr_info and friendsJohan Hovold2019-02-111-3/+3
* riscv: fixup max_low_pfn with PFN_DOWN.Guo Ren2019-01-231-1/+1
* arch: riscv: support kernel command line forcing when no DTB passedPaul Walmsley2019-01-071-1/+8
* RISC-V: Remove EARLY_PRINTK supportAnup Patel2018-12-171-28/+0
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-221-0/+10
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| * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-0/+6
| * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-221-0/+4
* | RISC-V: Use swiotlb on RV64 onlyZong Li2018-10-221-0/+3
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* RISCV: Fix end PFN for low memoryAtish Patra2018-10-021-1/+1
* riscv: Do not overwrite initrd_start and initrd_endGuenter Roeck2018-09-041-7/+0
* RISC-V: Add early printk support via the SBI consolePalmer Dabbelt2018-08-131-0/+27
* riscv: remove unnecessary of_platform_populate callRob Herring2018-07-041-5/+0
* riscv: add swiotlb supportChristoph Hellwig2018-05-191-0/+2
* Rename sbi_save to parse_dtb to improve code readabilityMichael Clark2018-02-201-1/+1
* riscv: add ZONE_DMA32Christoph Hellwig2018-01-301-0/+9
* RISC-V: Remove mem_end command line processingPalmer Dabbelt2018-01-301-19/+0
* RISC-V: Remove duplicate command-line parsing logicMichael Clark2018-01-301-16/+0
* RISC-V: Remove unused CONFIG_HVC_RISCV_SBI codePalmer Dabbelt2017-12-111-11/+0
* RISC-V: Export some expected symbols for modulesOlof Johansson2017-11-301-0/+2
* RISC-V: move empty_zero_page definition to C and export itOlof Johansson2017-11-301-0/+3
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+257
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