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path: root/arch/riscv/kernel/smp.c
Commit message (Expand)AuthorAgeFilesLines
* riscv: Use IPIs for remote cache/TLB flushes by defaultSamuel Holland2024-04-291-10/+1
* riscv: Use the same CPU operations for all CPUsSamuel Holland2024-01-041-1/+1
* riscv: Fix CPU feature detection with SMP disabledSamuel Holland2023-08-081-5/+0
* RISC-V: drop error print from riscv_hartid_to_cpuid()Conor Dooley2023-07-041-1/+0
* Merge tag 'smp-core-2023-04-27' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2023-04-281-2/+2
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| * treewide: Trace IPIs sent via smp_send_reschedule()Valentin Schneider2023-03-241-2/+2
* | RISC-V: Allow marking IPIs as suitable for remote FENCEsAnup Patel2023-04-081-1/+10
* | RISC-V: Treat IPIs as normal Linux IRQsAnup Patel2023-04-081-81/+79
* | RISC-V: Clear SIP bit only when using SBI IPI operationsAnup Patel2023-04-081-2/+0
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* riscv: kexec: Fixup crash_smp_send_stop without multi coresGuo Ren2022-11-291-2/+95
* Merge tag 'mm-nonmm-stable-2022-08-06-2' of git://git.kernel.org/pub/scm/linu...Linus Torvalds2022-08-071-6/+0
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| * profile: setup_profiling_timer() is moslty not implementedBen Dooks2022-07-291-6/+0
* | riscv: smp: Add 64bit hartid support on RV64Sunil V L2022-07-191-2/+2
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* RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=nSean Christopherson2022-01-091-10/+0
* irq: riscv: perform irqentry in entry codeMark Rutland2021-10-261-8/+1
* RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel2021-05-011-1/+1
* riscv: Constify sbi_ipi_opsJisheng Zhang2021-04-261-2/+2
* riscv: Mark some global variables __ro_after_initJisheng Zhang2021-04-261-2/+2
* riscv: Enable generic clockevent broadcastGuo Ren2021-03-161-0/+16
* RISC-V: Remove CLINT related code from timer and archAnup Patel2020-08-201-1/+0
* RISC-V: Add mechanism to provide custom IPI operationsAnup Patel2020-08-201-19/+24
* riscv: Support irq_work via self IPIsGreentime Hu2020-07-301-0/+15
* RISC-V: self-contained IPI handling routineAnup Patel2020-06-091-2/+9
* RISC-V: Export riscv_cpuid_to_hartid_mask() APIAnup Patel2020-05-041-0/+2
* riscv: fix the IPI missing issue in nommu modeGreentime Hu2020-03-181-1/+1
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-171-3/+13
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-1/+1
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+2
* RISC-V: Export kernel symbols for kvmAtish Patra2019-09-201-0/+1
* riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-051-0/+1
* riscv: optimize send_ipi_singleChristoph Hellwig2019-09-051-1/+7
* riscv: cleanup send_ipi_maskChristoph Hellwig2019-09-051-9/+7
* riscv: refactor the IPI codeChristoph Hellwig2019-09-051-24/+31
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-191-12/+1
* riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo2019-05-161-49/+0
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-161-1/+1
* RISC-V: Fix minor checkpatch issues.Atish Patra2019-05-161-2/+2
* RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra2019-04-301-0/+6
* RISC-V: Fixmap support and MM cleanupsPalmer Dabbelt2019-03-041-1/+1
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* | RISC-V: Allow hartid-to-cpuid function to fail.Atish Patra2019-03-041-1/+0
* | RISC-V: Move cpuid to hartid mapping to SMP.Atish Patra2019-03-041-0/+9
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* riscv: don't stop itself in smp_send_stopAndreas Schwab2019-01-071-7/+36
* RISC-V: Show IPI statsAnup Patel2018-10-221-7/+32
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-9/+15
* RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-221-0/+19
* RISC-V: simplify software interrupt / IPI codeChristoph Hellwig2018-08-131-4/+2
* RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt2017-12-011-0/+7
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| * RISC-V: Provide stub of setup_profiling_timer()Olof Johansson2017-11-301-0/+7
* | RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-301-0/+48
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* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+110
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