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path: root/arch/riscv/kernel/sys_hwprobe.c
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* RISC-V: hwprobe: Add SCALAR to misaligned perf definesEvan Green2024-08-141-5/+5
* RISC-V: hwprobe: Add MISALIGNED_PERF keyEvan Green2024-08-141-0/+1
* RISC-V: Provide the frequency of time CSR via hwprobePalmer Dabbelt2024-07-261-0/+5
* RISC-V: hwprobe: sort EXT_KEY()s in hwprobe_isa_ext0() alphabeticallyConor Dooley2024-07-221-22/+21
* Merge patch series "riscv: Apply Zawrs when available"Palmer Dabbelt2024-07-121-0/+1
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| * riscv: hwprobe: export Zawrs ISA extensionAndrew Jones2024-07-121-0/+1
* | riscv: hwprobe: export highest virtual userspace addressClément Léger2024-07-111-0/+4
* | riscv: hwprobe: export Zcmop ISA extensionClément Léger2024-06-261-0/+1
* | riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensionsClément Léger2024-06-261-0/+4
* | riscv: hwprobe: export Zimop ISA extensionClément Léger2024-06-261-0/+1
* | riscv: vector: adjust minimum Vector requirement to ZVE32XAndy Chiu2024-05-301-1/+5
* | riscv: hwprobe: add zve Vector subextensions into hwprobe interfaceAndy Chiu2024-05-301-0/+5
* | riscv: hwprobe: export Zihintpause ISA extensionClément Léger2024-04-281-0/+1
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* riscv: Set unaligned access speed at compile timeCharlie Jenkins2024-03-131-0/+13
* Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt2024-01-091-0/+3
* Merge patch series "RISC-V: hwprobe: Introduce which-cpus"Palmer Dabbelt2024-01-091-0/+33
* RISC-V: hwprobe: Introduce which-cpus flagAndrew Jones2024-01-031-4/+90
* RISC-V: Move the hwprobe syscall to its own fileAndrew Jones2024-01-031-0/+289
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 19:28:55 +0000