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* riscv: Fix SMP when shadow call stacks are enabledSamuel Holland2023-12-061-1/+1
* riscv: fix misaligned access handling of C.SWSP and C.SDSPClément Léger2023-12-061-4/+2
* RISC-V: hwprobe: Always use u64 for extension bitsAndrew Jones2023-12-061-1/+1
* Support rv32 ULEB128 testCharlie Jenkins2023-12-061-4/+4
* riscv: Correct type casting in module loadingCharlie Jenkins2023-12-041-2/+2
* riscv: Safely remove entries from relocation listCharlie Jenkins2023-12-041-28/+82
* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-1040-336/+1599
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| * Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...Palmer Dabbelt2023-11-094-32/+20
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| * \ Merge patch series "Linux RISC-V AIA Preparatory Series"Palmer Dabbelt2023-11-081-5/+6
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| | * | RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTsAnup Patel2023-11-081-5/+6
| * | | RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-072-20/+77
| * | | RISC-V: Remove __init on unaligned_emulation_finish()Evan Green2023-11-071-1/+1
| * | | RISC-V: Show accurate per-hart isa in /proc/cpuinfoEvan Green2023-11-071-4/+18
| * | | RISC-V: Don't rely on positional structure initializationPalmer Dabbelt2023-11-071-60/+65
| * | | Merge patch series "riscv: Add remaining module relocations and tests"Palmer Dabbelt2023-11-0716-104/+864
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| | * | | riscv: Add tests for riscv module loadingCharlie Jenkins2023-11-0715-0/+365
| | * | | riscv: Add remaining module relocationsCharlie Jenkins2023-11-071-29/+419
| | * | | riscv: Avoid unaligned access when relocating modulesEmil Renner Berthing2023-11-071-76/+81
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| * | | riscv: kernel: Use correct SYM_DATA_*() macro for dataClément Léger2023-11-061-5/+4
| * | | riscv: Use SYM_*() assembly macros instead of deprecated onesClément Léger2023-11-0612-48/+44
| * | | riscv: use ".L" local labels in assembly when applicableClément Léger2023-11-063-17/+17
| * | | Merge patch series "riscv: tlb flush improvements"Palmer Dabbelt2023-11-061-22/+10
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| | * | | riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2023-11-061-22/+10
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| * | | Merge patch series "riscv: vdso.lds.S: some improvement"Palmer Dabbelt2023-11-051-17/+13
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| | * | | riscv: vdso.lds.S: remove hardcoded 0x800 .text start addrJisheng Zhang2023-11-051-9/+8
| | * | | riscv: vdso.lds.S: merge .data section into .rodata sectionJisheng Zhang2023-11-051-8/+7
| | * | | riscv: vdso.lds.S: drop __alt_start and __alt_end symbolsJisheng Zhang2023-11-051-2/+0
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| * | | riscv: add userland instruction dump to RISC-V splatsYunhui Cui2023-11-051-3/+18
| * | | riscv: kprobes: allow writing to x0Nam Cao2023-11-051-1/+1
| * | | riscv: provide riscv-specific is_trap_insn()Nam Cao2023-11-051-0/+6
| * | | riscv: don't probe unaligned access speed if already doneJisheng Zhang2023-11-051-0/+4
| * | | riscv: signal: handle syscall restart before get_signalHaorong Lu2023-11-051-39/+46
| * | | Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-057-59/+474
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| | * | | riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger2023-11-012-0/+24
| | * | | riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-013-1/+61
| | * | | riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger2023-11-011-1/+1
| | * | | riscv: add support for sysctl unaligned_enabled controlClément Léger2023-11-011-0/+9
| | * | | riscv: add floating point insn support to misaligned access emulationClément Léger2023-11-012-4/+269
| | * | | riscv: report perf event for misaligned faultClément Léger2023-11-011-0/+5
| | * | | riscv: add support for misaligned trap handling in S-modeClément Léger2023-11-013-23/+107
| | * | | riscv: remove unused functions in traps_misaligned.cClément Léger2023-11-011-39/+7
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* | | | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-0814-222/+275
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| * | | RISC-V: hwprobe: Fix vDSO SIGSEGVAndrew Jones2023-11-021-1/+1
| * | | Merge patch series "riscv: SCS support"Palmer Dabbelt2023-11-027-171/+112
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| | * | | riscv: Use separate IRQ shadow call stacksSami Tolvanen2023-10-272-0/+28
| | * | | riscv: Implement Shadow Call StackSami Tolvanen2023-10-274-1/+19
| | * | | riscv: Move global pointer loading to a macroSami Tolvanen2023-10-273-20/+6
| | * | | riscv: Deduplicate IRQ stack switchingSami Tolvanen2023-10-274-55/+47
| | * | | riscv: VMAP_STACK overflow detection thread-safeDeepak Gupta2023-10-273-95/+12
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| * | | Merge patch series "RISC-V: ACPI improvements"Palmer Dabbelt2023-10-311-2/+85
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