Commit message (Expand) | Author | Age | Files | Lines | |
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* | RISC-V: Build tishift only on 64-bit | Zong Li | 2018-10-22 | 1 | -1/+2 |
* | RISC-V: implement __lshrti3. | Alex Guo | 2018-08-13 | 2 | -0/+43 |
* | RISC-V: Make our port sparse-clean | Palmer Dabbelt | 2018-06-11 | 1 | -2/+4 |
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| * | riscv: split the declaration of __copy_user | Luc Van Oostenryck | 2018-06-09 | 1 | -2/+4 |
* | | riscv: Fix the bug in memory access fixup code | Alan Kao | 2018-06-04 | 1 | -4/+9 |
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* | RISC-V: Export some expected symbols for modules | Olof Johansson | 2017-11-30 | 1 | -0/+1 |
* | RISC-V: Build Infrastructure | Palmer Dabbelt | 2017-09-26 | 1 | -0/+6 |
* | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 2017-09-26 | 1 | -0/+110 |
* | RISC-V: Generic library routines and assembly | Palmer Dabbelt | 2017-09-26 | 4 | -0/+390 |