summaryrefslogtreecommitdiffstats
path: root/arch/riscv
Commit message (Expand)AuthorAgeFilesLines
* riscv: Bump COMMAND_LINE_SIZE value to 1024Alexandre Ghiti2023-04-051-0/+8
* RISC-V: time: initialize hrtimer based broadcast clock event deviceConor Dooley2023-03-111-0/+3
* riscv: Fixup race condition on PG_dcache_clean in flush_icache_pteGuo Ren2023-02-221-1/+3
* riscv: disable generation of unwind tablesAndreas Schwab2023-02-221-0/+3
* exit: Add and use make_task_dead.Eric W. Biederman2023-02-062-2/+2
* riscv: uaccess: fix type of 0 variable on error in get_user()Ben Dooks2023-01-181-1/+1
* RISC-V: vdso: Do not add missing symbols to version section in linker scriptNathan Chancellor2022-12-082-0/+5
* riscv: process: fix kernel info leakageJisheng Zhang2022-11-251-0/+2
* riscv: fix build with binutils 2.38Aurelien Jarno2022-10-261-2/+9
* riscv: Allow PROT_WRITE-only mmap()Andrew Bresticker2022-10-261-3/+0
* RISC-V: Add fast call path of crash_kexec()Xianting Tian2022-08-251-0/+4
* riscv: mmap with PROT_WRITE but no PROT_READ is invalidCeleste Liu2022-08-251-3/+2
* riscv: add as-options for modules with assembly compontentsBen Dooks2022-07-291-0/+1
* RISC-V: fix barrier() use in <vdso/processor.h>Randy Dunlap2022-06-251-0/+2
* riscv module: remove (NOLOAD)Fangrui Song2022-04-151-3/+3
* riscv: Fix auipc+jalr relocation range checksEmil Renner Berthing2022-03-161-5/+16
* arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where neededArnd Bergmann2021-11-061-0/+2
* drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()Thomas Gleixner2021-09-261-5/+2
* riscv: Workaround mcount name prior to clang-13Nathan Chancellor2021-05-222-7/+17
* riscv,entry: fix misaligned base for excp_vect_tableZihao Yu2021-04-161-0/+1
* riscv: virt_addr_valid must check the address belongs to linear mappingAlexandre Ghiti2021-02-231-1/+4
* riscv: Fix kernel time_init()Damien Le Moal2021-01-271-0/+3
* riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFOZong Li2020-11-051-0/+3
* RISC-V: Take text_mutex in ftrace_init_nop()Palmer Dabbelt2020-10-012-0/+26
* RISC-V: Upgrade smp_mb__after_spinlock() to iorw,iorwPalmer Dabbelt2020-07-291-1/+9
* riscv: use 16KB kernel stack on 64-bitAndreas Schwab2020-07-221-0/+4
* RISC-V: Don't allow write+exec only page mapping request in mmapYash Shah2020-06-301-0/+6
* riscv/atomic: Fix sign extension for RV64INathan Huckleberry2020-06-301-4/+4
* riscv: stacktrace: Fix undefined reference to `walk_stackframe'Kefeng Wang2020-06-031-1/+1
* riscv: set max_pfn to the PFN of the last pageVincent Chen2020-05-271-0/+2
* riscv: fix vdso build with lldIlie Halip2020-05-201-3/+3
* riscv: avoid the PIC offset of static percpu data in module beyond 2G limitsVincent Chen2020-03-251-0/+16
* riscv: delete temporary filesIlie Halip2020-02-051-1/+2
* riscv: ftrace: correct the condition logic in function graph tracerZong Li2020-01-091-1/+1
* RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen2019-12-011-1/+1
* riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen2019-10-111-1/+5
* riscv: remove unused variable in ftraceDavid Abdurachmanov2019-09-161-1/+0
* riscv: Make __fstate_clean() work correctly.Vincent Chen2019-08-251-1/+1
* riscv: Fix udelay in RV32.Nick Hu2019-07-141-1/+1
* riscv: mm: synchronize MMU after pte changeShihPo Hung2019-06-251-0/+13
* riscv: fix accessing 8-byte variable from RV32Alan Kao2019-05-081-1/+1
* riscv: Fix syscall_get_arguments() and syscall_set_arguments()Dmitry V. Levin2019-04-171-5/+7
* riscv: Adjust mmap base address at a third of task sizeAlexandre Ghiti2019-03-131-1/+1
* riscv: fixup max_low_pfn with PFN_DOWN.Guo Ren2019-03-132-2/+3
* riscv: Add pte bit to distinguish swap from invalidStefan O'Rear2019-02-202-4/+10
* riscv: fix trace_sys_exit hookDavid Abdurachmanov2019-02-201-1/+1
* riscv: fix warning in arch/riscv/include/asm/module.hDavid Abdurachmanov2018-12-131-0/+1
* riscv/function_graph: Simplify with function_graph_enter()Steven Rostedt (VMware)2018-12-051-12/+2
* RISC-V: Silence some module warnings on 32-bitOlof Johansson2018-12-011-6/+6
* riscv: add missing vdso_install targetDavid Abdurachmanov2018-12-011-0/+4
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-04 08:44:19 +0000