summaryrefslogtreecommitdiffstats
path: root/arch/riscv
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-1081-683/+2509
|\
| * riscv: Optimize bitops with Zbb extensionXiao Wang2023-11-091-3/+251
| * riscv: Rearrange hwcap.h and cpufeature.hXiao Wang2023-11-0912-100/+93
| * Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...Palmer Dabbelt2023-11-099-35/+67
| |\
| * \ Merge patch series "Linux RISC-V AIA Preparatory Series"Palmer Dabbelt2023-11-081-5/+6
| |\ \
| | * | RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTsAnup Patel2023-11-081-5/+6
| * | | Merge patch series "riscv: Fix set_memory_XX() and set_direct_map_XX()"Palmer Dabbelt2023-11-082-46/+236
| |\ \ \
| | * | | riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear m...Alexandre Ghiti2023-11-081-40/+230
| | * | | riscv: Don't use PGD entries for the linear mappingAlexandre Ghiti2023-11-081-6/+6
| | |/ /
| * | | RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-073-21/+77
| * | | RISC-V: Remove __init on unaligned_emulation_finish()Evan Green2023-11-071-1/+1
| * | | RISC-V: Show accurate per-hart isa in /proc/cpuinfoEvan Green2023-11-071-4/+18
| * | | RISC-V: Don't rely on positional structure initializationPalmer Dabbelt2023-11-071-60/+65
| * | | Merge patch series "riscv: Add remaining module relocations and tests"Palmer Dabbelt2023-11-0718-105/+869
| |\ \ \
| | * | | riscv: Add tests for riscv module loadingCharlie Jenkins2023-11-0716-0/+366
| | * | | riscv: Add remaining module relocationsCharlie Jenkins2023-11-072-30/+423
| | * | | riscv: Avoid unaligned access when relocating modulesEmil Renner Berthing2023-11-071-76/+81
| | |/ /
| * | | riscv: split cache ops out of dma-noncoherent.cChristoph Hellwig2023-11-073-15/+18
| * | | riscv: select ARCH_PROC_KCORE_TEXTAndreas Schwab2023-11-061-0/+3
| * | | riscv: kernel: Use correct SYM_DATA_*() macro for dataClément Léger2023-11-061-5/+4
| * | | riscv: Use SYM_*() assembly macros instead of deprecated onesClément Léger2023-11-0617-74/+60
| * | | riscv: use ".L" local labels in assembly when applicableClément Léger2023-11-064-44/+44
| * | | riscv: boot: Fix creation of loader.binGeert Uytterhoeven2023-11-061-0/+1
| * | | Merge patch series "riscv: tlb flush improvements"Palmer Dabbelt2023-11-065-95/+144
| |\ \ \
| | * | | riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti2023-11-062-15/+30
| | * | | riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2023-11-064-81/+72
| | * | | riscv: Improve flush_tlb_range() for hugetlb pagesAlexandre Ghiti2023-11-061-1/+28
| | * | | riscv: Improve tlb_flush()Alexandre Ghiti2023-11-063-1/+17
| | |/ /
| * | | riscv: mm: update T-Head memory type definitionsJisheng Zhang2023-11-051-5/+9
| * | | Merge patch series "riscv: vdso.lds.S: some improvement"Palmer Dabbelt2023-11-051-17/+13
| |\ \ \
| | * | | riscv: vdso.lds.S: remove hardcoded 0x800 .text start addrJisheng Zhang2023-11-051-9/+8
| | * | | riscv: vdso.lds.S: merge .data section into .rodata sectionJisheng Zhang2023-11-051-8/+7
| | * | | riscv: vdso.lds.S: drop __alt_start and __alt_end symbolsJisheng Zhang2023-11-051-2/+0
| | |/ /
| * | | riscv: add userland instruction dump to RISC-V splatsYunhui Cui2023-11-051-3/+18
| * | | riscv: kprobes: allow writing to x0Nam Cao2023-11-051-1/+1
| * | | riscv: provide riscv-specific is_trap_insn()Nam Cao2023-11-051-0/+6
| * | | Merge patch series "Improve PTDUMP and introduce new fields"Palmer Dabbelt2023-11-052-21/+36
| |\ \ \
| | * | | riscv: Introduce NAPOT field to PTDUMPYu Chien Peter Lin2023-11-051-0/+4
| | * | | riscv: Introduce PBMT field to PTDUMPYu Chien Peter Lin2023-11-051-0/+16
| | * | | riscv: Improve PTDUMP to show RSW with non-zero valueYu Chien Peter Lin2023-11-052-22/+17
| | |/ /
| * | | RISC-V: capitalise CMO op macrosConor Dooley2023-11-055-29/+29
| * | | riscv: don't probe unaligned access speed if already doneJisheng Zhang2023-11-051-0/+4
| * | | riscv: defconfig : add CONFIG_MMC_DW for starfiveJinyu Tang2023-11-051-0/+2
| * | | riscv: signal: handle syscall restart before get_signalHaorong Lu2023-11-051-39/+46
| * | | Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-0511-59/+524
| |\ \ \
| | * | | riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger2023-11-013-0/+33
| | * | | riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-014-1/+79
| | * | | riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger2023-11-011-1/+1
| | * | | riscv: add support for sysctl unaligned_enabled controlClément Léger2023-11-012-0/+10
| | * | | riscv: add floating point insn support to misaligned access emulationClément Léger2023-11-012-4/+269
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 16:02:08 +0000