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* RISC-V: recognize S/U mode bits in print_isaPatrick Stählin2018-11-201-3/+6
* riscv: add asm/unistd.h UAPI headerDavid Abdurachmanov2018-11-202-10/+21
* riscv: fix warning in arch/riscv/include/asm/module.hDavid Abdurachmanov2018-11-201-0/+1
* RISC-V: Build flat and compressed kernel imagesAnup Patel2018-11-206-2/+120
* RISC-V: Fix raw_copy_{to,from}_user()Olof Johansson2018-11-201-2/+2
* RISC-V: Silence some module warnings on 32-bitOlof Johansson2018-11-121-6/+6
* RISC-V: lib: Fix build error for 64-bitOlof Johansson2018-11-121-1/+1
* riscv: add missing vdso_install targetDavid Abdurachmanov2018-11-121-0/+4
* riscv: fix spacing in struct pt_regsDavid Abdurachmanov2018-11-121-2/+2
* RISC-V: defconfig: Enable printk timestampsAnup Patel2018-11-121-0/+1
* RISC-V: refresh defconfigAnup Patel2018-11-011-8/+8
* Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-313-7/+5
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| * lib: Remove umoddi3 and udivmoddi4Palmer Dabbelt2018-10-311-1/+0
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| | * Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"Palmer Dabbelt2018-10-311-1/+0
| * | Move EM_RISCV into elf-em.hPalmer Dabbelt2018-10-311-3/+0
| * | RISC-V: properly determine hardware capsAndreas Schwab2018-10-311-3/+5
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* | mm: remove include/linux/bootmem.hMike Rapoport2018-10-311-2/+1
* | memblock: rename free_all_bootmem to memblock_free_allMike Rapoport2018-10-311-1/+1
* | mm: remove CONFIG_HAVE_MEMBLOCKMike Rapoport2018-10-311-1/+0
* | mm: remove CONFIG_NO_BOOTMEMMike Rapoport2018-10-311-1/+0
* | treewide: remove current_text_addrNick Desaulniers2018-10-311-6/+0
* | Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-2527-238/+679
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| * RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-2210-62/+245
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| | * RISC-V: Show IPI statsAnup Patel2018-10-223-7/+49
| | * RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel2018-10-221-4/+6
| | * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-226-25/+58
| | * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-223-1/+46
| | * RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra2018-10-221-2/+3
| | * RISC-V: Use mmgrab()Palmer Dabbelt2018-10-221-1/+2
| | * RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt2018-10-221-4/+5
| | * RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-223-4/+7
| | * RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-221-10/+4
| | * RISC-V: Disable preemption before enabling interruptsAtish Patra2018-10-221-1/+5
| | * RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt2018-10-221-0/+4
| | * RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt2018-10-221-7/+61
| | * RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt2018-10-221-7/+0
| | * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-222-3/+2
| * | RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt2018-10-224-2/+7
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| | * | RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen2018-10-221-1/+1
| | * | RISC-V: Select GENERIC_LIB_UMODDI3 on RV32Zong Li2018-10-221-0/+1
| | * | RISC-V: Use swiotlb on RV64 onlyZong Li2018-10-221-0/+3
| | * | RISC-V: Build tishift only on 64-bitZong Li2018-10-221-1/+2
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| * | riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-229-127/+196
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| | * | Auto-detect whether a FPU existsAlan Kao2018-10-224-7/+19
| | * | Allow to disable FPU supportAlan Kao2018-10-226-3/+29
| | * | Cleanup ISA string settingAlan Kao2018-10-221-11/+8
| | * | Refactor FPU code in signal setup/return proceduresAlan Kao2018-10-221-27/+41
| | * | Extract FPU context operations from entry.SAlan Kao2018-10-223-87/+107
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| * | RISC-V: Cosmetic menuconfig changesNick Kossifidis2018-10-222-36/+39
| * | riscv: move GCC version check for ARCH_SUPPORTS_INT128 to KconfigMasahiro Yamada2018-10-222-2/+1
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