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path: root/arch/x86/events/perf_event.h
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* perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guestLike Xu2021-08-121-1/+2
* perf/x86/amd: Constrain Large Increment per Cycle eventsKim Phillips2020-02-241-0/+2
* perf/x86/intel: Support PEBS output to PTAlexander Shishkin2019-08-281-0/+17
* Merge tag 'v5.2' into perf/core, to pick up fixesIngo Molnar2019-07-081-20/+1
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| * perf/x86: Remove pmu->pebs_no_xmm_regsKan Liang2019-06-241-2/+1
| * perf/x86: Clean up PEBS_XMM_REGSKan Liang2019-06-241-18/+0
* | perf/x86: Use update attribute groups for default attributesJiri Olsa2019-06-031-3/+0
* | perf/x86: Use update attribute groups for capsJiri Olsa2019-06-031-1/+0
* | perf/x86: Use the new pmu::update_attrs attribute groupJiri Olsa2019-06-031-1/+1
* | perf/x86: Get rid of x86_pmu::event_attrsJiri Olsa2019-06-031-1/+0
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* perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* maskingStephane Eranian2019-05-101-2/+2
* perf/x86/intel: Add Icelake supportKan Liang2019-04-161-0/+2
* perf/x86: Support constraint rangesPeter Zijlstra2019-04-161-6/+37
* perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles themAndi Kleen2019-04-161-0/+1
* perf/x86/intel: Support adaptive PEBS v4Kan Liang2019-04-161-1/+10
* perf/x86: Support outputting XMM registersKan Liang2019-04-161-1/+20
* perf/x86/intel: Force resched when TFA sysctl is modifiedStephane Eranian2019-04-161-0/+1
* Merge branch 'perf/urgent' into perf/core, to pick up fixesIngo Molnar2019-04-161-19/+19
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| * perf/x86: Fix incorrect PEBS_REGSKan Liang2019-04-161-19/+19
* | perf/x86: Remove PERF_X86_EVENT_COMMITTEDPeter Zijlstra2019-04-031-10/+9
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* perf/x86: Fixup typo in stub functionsPeter Zijlstra2019-03-151-2/+2
* Merge branch 'x86-tsx-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2019-03-121-3/+14
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| * perf/x86/intel: Implement support for TSX Force AbortPeter Zijlstra (Intel)2019-03-061-0/+6
| * perf/x86/intel: Make cpuc allocations consistentPeter Zijlstra (Intel)2019-03-061-3/+8
* | Merge branch 'linus' into perf/core, to pick up fixesIngo Molnar2019-02-281-2/+14
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| * perf/x86: Add check_period PMU callbackJiri Olsa2019-02-111-2/+14
* | perf/x86/kvm: Avoid unnecessary work in guest filteringAndi Kleen2019-02-111-7/+8
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* perf/x86/intel: Add generic branch tracing check to intel_pmu_has_bts()Jiri Olsa2018-11-221-4/+9
* perf/x86/intel: Add a separate Arch Perfmon v4 PMI handlerAndi Kleen2018-10-021-1/+3
* perf/x86/intel: Introduce PMU flag for Extended PEBSKan Liang2018-07-251-0/+1
* perf/x86/intel/lbr: Optimize context switches for the LBR call stackKan Liang2018-06-211-0/+4
* perf/x86/intel/lbr: Fix incomplete LBR call stackKan Liang2018-06-211-0/+1
* Merge branch 'perf/urgent' into perf/core, to pick up fixesIngo Molnar2018-03-241-3/+3
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| * perf/x86/intel: Rename confusing 'freerunning PEBS' API and implementation to...Kan Liang2018-03-201-3/+3
* | perf/x86/intel/ds: Introduce ->read() function for auto-reload events and flu...Kan Liang2018-03-091-0/+2
* | perf/x86: Introduce a ->read() callback in 'struct x86_pmu'Kan Liang2018-03-091-0/+1
* | perf/x86/intel: Fix large period handling on Broadwell CPUsKan Liang2018-03-091-1/+1
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* x86/events/intel/ds: Add PERF_SAMPLE_PERIOD into PEBS_FREERUNNING_FLAGSJiri Olsa2018-02-051-1/+2
* x86/events/intel/ds: Map debug buffers in cpu_entry_areaHugh Dickins2017-12-231-0/+2
* x86/cpu_entry_area: Add debugstore entries to cpu_entry_areaThomas Gleixner2017-12-231-19/+2
* perf/x86: Enable free running PEBS for REGS_USER/INTRAndi Kleen2017-12-171-1/+23
* perf/core, x86: Add PERF_SAMPLE_PHYS_ADDRKan Liang2017-08-291-1/+1
* perf/x86: Export some PMU attributes in caps/ directoryAndi Kleen2017-08-251-0/+3
* perf/x86: Fix data source decoding for SkylakeAndi Kleen2017-08-251-0/+2
* perf/x86: Move Nehalem PEBS code to flagAndi Kleen2017-08-251-1/+2
* perf/x86/intel: Add Goldmont Plus CPU PMU supportKan Liang2017-07-181-0/+2
* perf/x86: Add sysfs entry to freeze counters on SMIKan Liang2017-05-231-0/+3
* perf/x86: Fix spurious NMI with PEBS Load Latency eventKan Liang2017-04-141-0/+1
* perf/x86: Fix exclusion of BTS and LBR for GoldmontAndi Kleen2016-12-111-1/+1
* perf/x86/intel: Cure bogus unwind from PEBS entriesPeter Zijlstra2016-11-221-1/+1
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