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* x86/entry: __always_inline irqflags for noinstrPeter Zijlstra2020-06-111-10/+10
* x86/entry: __always_inline debugreg for noinstrPeter Zijlstra2020-06-111-3/+3
* x86/idt: Consolidate idt functionalityThomas Gleixner2020-06-111-15/+2
* x86/entry: Clarify irq_{enter,exit}_rcu()Peter Zijlstra2020-06-111-2/+0
* x86/entry: Remove DBn stacksPeter Zijlstra2020-06-111-9/+3
* x86/entry: Remove debug IDT frobbingPeter Zijlstra2020-06-112-52/+1
* x86/entry: Optimize local_db_save() for virtPeter Zijlstra2020-06-111-1/+4
* x86/entry: Introduce local_db_{save,restore}()Peter Zijlstra2020-06-111-0/+30
* x86/entry: Remove the TRACE_IRQS cruftThomas Gleixner2020-06-111-10/+0
* x86/entry: Remove the apic/BUILD interrupt leftoversThomas Gleixner2020-06-111-12/+0
* x86/entry: Convert reschedule interrupt to IDTENTRY_SYSVEC_SIMPLEThomas Gleixner2020-06-115-26/+2
* x86/entry: Convert XEN hypercall vector to IDTENTRY_SYSVECThomas Gleixner2020-06-111-0/+4
* x86/entry: Convert various hypervisor vectors to IDTENTRY_SYSVECThomas Gleixner2020-06-114-44/+10
* x86/entry: Convert KVM vectors to IDTENTRY_SYSVEC*Thomas Gleixner2020-06-114-14/+6
* x86/entry: Convert various system vectorsThomas Gleixner2020-06-117-56/+24
* x86/entry: Convert SMP system vectors to IDTENTRY_SYSVECThomas Gleixner2020-06-114-11/+7
* x86/entry: Convert APIC interrupts to IDTENTRY_SYSVECThomas Gleixner2020-06-115-13/+8
* x86/entry: Provide IDTENTRY_SYSVECThomas Gleixner2020-06-111-0/+79
* x86/entry: Use idtentry for interruptsThomas Gleixner2020-06-113-4/+8
* x86/entry: Add IRQENTRY_IRQ macroThomas Gleixner2020-06-111-0/+49
* x86/irq: Rework handle_irq() for 64-bitThomas Gleixner2020-06-111-1/+1
* x86/irq: Convey vector as argument and not in ptregsThomas Gleixner2020-06-115-3/+53
* x86/irq: Use generic irq_regs implementationThomas Gleixner2020-06-111-32/+0
* x86/entry: Remove the transition leftoversThomas Gleixner2020-06-111-3/+3
* x86/entry: Switch page fault exception to IDTENTRY_RAWThomas Gleixner2020-06-112-12/+2
* x86/entry: Switch XEN/PV hypercall entry to IDTENTRYThomas Gleixner2020-06-111-0/+34
* x86/entry: Provide helpers for executing on the irqstackThomas Gleixner2020-06-111-0/+53
* x86/entry: Clean up idtentry_enter/exit() leftoversThomas Gleixner2020-06-111-11/+1
* x86/idtentry: Switch to conditional RCU handlingThomas Gleixner2020-06-111-4/+6
* x86/entry: Provide idtentry_enter/exit_user()Thomas Gleixner2020-06-111-0/+3
* x86/entry: Provide idtentry_entry/exit_cond_rcu()Thomas Gleixner2020-06-111-2/+12
* x86/entry: Convert double fault exception to IDTENTRY_DFThomas Gleixner2020-06-112-5/+3
* x86/idtentry: Provide IDTENTRY_DFThomas Gleixner2020-06-111-0/+87
* x86/idtentry: Provide IDTRENTRY_NOIST variants for #DB and #MCThomas Gleixner2020-06-111-2/+17
* x86/entry: Convert Debug exception to IDTENTRY_DBThomas Gleixner2020-06-112-3/+4
* x86/nmi: Protect NMI entry against instrumentationThomas Gleixner2020-06-111-4/+4
* x86/entry: Convert NMI to IDTENTRY_NMIThomas Gleixner2020-06-112-3/+4
* x86/idtentry: Provide IDTENTRY_XEN for XEN/PVThomas Gleixner2020-06-111-0/+16
* x86/entry: Convert Machine Check to IDTENTRY_ISTThomas Gleixner2020-06-113-8/+5
* x86/idtentry: Provide IDTENTRY_ISTThomas Gleixner2020-06-111-0/+54
* x86/entry: Convert INT3 exception to IDTENTRY_RAWThomas Gleixner2020-06-112-3/+3
* x86/idtentry: Provide IDTENTRY_RAWThomas Gleixner2020-06-111-0/+31
* x86/int3: Ensure that poke_int3_handler() is not tracedThomas Gleixner2020-06-112-5/+8
* x86/entry/32: Convert IRET exception to IDTENTRY_SWThomas Gleixner2020-06-112-3/+10
* x86/entry: Convert SIMD coprocessor error exception to IDTENTRYThomas Gleixner2020-06-112-3/+1
* x86/entry: Convert Alignment check exception to IDTENTRYThomas Gleixner2020-06-112-3/+1
* x86/entry: Convert Coprocessor error exception to IDTENTRYThomas Gleixner2020-06-112-3/+1
* x86/entry: Convert Spurious interrupt bug exception to IDTENTRYThomas Gleixner2020-06-112-3/+1
* x86/entry: Convert General protection exception to IDTENTRYThomas Gleixner2020-06-112-3/+1
* x86/entry: Convert Stack segment exception to IDTENTRYThomas Gleixner2020-06-112-3/+1
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