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* riscv: Fix build errors using binutils2.37 toolchainsMingzheng Xing2023-08-241-4/+4
* Merge patch series "riscv: fix ptrace and export VLENB"Palmer Dabbelt2023-08-233-70/+3
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| * RISC-V: vector: export VLENB csr in __sc_riscv_v_stateAndy Chiu2023-08-222-1/+3
| * RISC-V: Remove ptrace support for vectorsPalmer Dabbelt2023-08-221-69/+0
* | riscv: Handle zicsr/zifencei issue between gcc and binutilsMingzheng Xing2023-08-162-14/+26
* | riscv: uaccess: Return the number of bytes effectively not copiedAlexandre Ghiti2023-08-161-4/+7
* | riscv: stack: Fixup independent softirq stack for CONFIG_FRAME_POINTER=nGuo Ren2023-08-161-0/+3
* | riscv: stack: Fixup independent irq stack for CONFIG_FRAME_POINTER=nGuo Ren2023-08-161-0/+3
* | riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr()Nam Cao2023-08-161-2/+13
* | riscv: entry: set a0 = -ENOSYS only when syscall != -1Celeste Liu2023-08-161-3/+3
* | riscv: Implement flush_cache_vmap()Alexandre Ghiti2023-08-101-0/+4
* | riscv: Do not allow vmap pud mappings for 3-level page tableAlexandre Ghiti2023-08-101-1/+3
* | riscv: mm: fix 2 instances of -Wmissing-variable-declarationsNick Desaulniers2023-08-083-5/+7
* | riscv,mmio: Fix readX()-to-delay() orderingAndrea Parri2023-08-081-8/+8
* | riscv: Fix CPU feature detection with SMP disabledSamuel Holland2023-08-082-5/+5
* | riscv: Start of DRAM should at least be aligned on PMD size for the direct ma...Alexandre Ghiti2023-08-041-1/+6
* | Merge patch series "RISC-V: Fix a few kexec_file_load(2) failures"Palmer Dabbelt2023-08-041-1/+2
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| * | riscv/kexec: load initrd high in available memoryTorsten Duwe2023-08-041-1/+1
| * | riscv/kexec: handle R_RISCV_CALL_PLT relocation typeTorsten Duwe2023-08-041-0/+1
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* | riscv: Export va_kernel_pa_offset in vmcoreinfoSong Shuai2023-08-021-0/+2
* | RISC-V: ACPI: Fix acpi_os_ioremap to return iomem addressSunil V L2023-08-022-3/+3
* | RISC-V: Don't include Zicsr or Zifencei in I from ACPIPalmer Dabbelt2023-07-121-7/+2
* | riscv: mm: fix truncation warning on RV32Jisheng Zhang2023-07-121-1/+1
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* Merge tag 'x86_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-07-091-0/+1
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| * x86/xen: Fix secondary processors' FPU initializationJuergen Gross2023-07-051-0/+1
* | Merge tag 'x86-core-2023-07-09' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2023-07-091-0/+8
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| * | x86/smp: Don't send INIT to boot CPUThomas Gleixner2023-07-071-0/+8
* | | Merge tag 'mips_6.5_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/...Linus Torvalds2023-07-0910-53/+46
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| * | | MIPS: kvm: Fix build error with KVM_MIPS_DEBUG_COP0_COUNTERS enabledThomas Bogendoerfer2023-07-071-2/+2
| * | | MIPS: dts: add missing space before {Krzysztof Kozlowski2023-07-062-2/+2
| * | | MIPS: Loongson: Fix build error when make modules_installHuacai Chen2023-07-031-7/+3
| * | | MIPS: KVM: Fix NULL pointer dereferenceHuacai Chen2023-07-035-36/+36
| * | | MIPS: Loongson: Fix cpu_probe_loongson() againHuacai Chen2023-07-031-6/+3
* | | | Merge tag 'riscv-for-linus-6.5-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-07-0715-29/+86
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| * \ \ \ Merge patch series "riscv: some CMO alternative related clean up"Palmer Dabbelt2023-07-063-7/+10
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| | * | | | riscv: mm: mark noncoherent_supported as __ro_after_initJisheng Zhang2023-07-061-1/+1
| | * | | | riscv: mm: mark CBO relate initialization funcs as __initJisheng Zhang2023-07-061-4/+4
| | * | | | riscv: errata: thead: only set cbom size & noncoherent during bootJisheng Zhang2023-07-061-2/+5
| * | | | | riscv: Select HAVE_ARCH_USERFAULTFD_MINORSamuel Holland2023-07-061-0/+1
| * | | | | risc-v: Fix order of IPI enablement vs RCU startupMarc Zyngier2023-07-051-2/+3
| * | | | | mm: riscv: fix an unsafe pte read in huge_pte_alloc()John Hubbard2023-07-051-1/+5
| * | | | | RISC-V: drop error print from riscv_hartid_to_cpuid()Conor Dooley2023-07-041-1/+0
| * | | | | riscv: Discard vector state on syscallsBjörn Töpel2023-07-042-0/+36
| * | | | | riscv: move memblock_allow_resize() after linear mapping is readyWoody Zhang2023-07-041-1/+3
| * | | | | riscv: Enable ARCH_SUSPEND_POSSIBLE for s2idleSong Shuai2023-07-041-0/+3
| * | | | | riscv: vdso: include vdso/vsyscall.h for vdso_dataBen Dooks2023-07-041-0/+1
| * | | | | riscv: vector: clear V-reg in the first-use trapAndy Chiu2023-07-011-0/+1
| * | | | | riscv: vector: only enable interrupts in the first-use trapAndy Chiu2023-07-011-1/+7
| * | | | | Merge patch series "riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION"Palmer Dabbelt2023-07-013-15/+11
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| | * | | | | riscv: disable HAVE_LD_DEAD_CODE_DATA_ELIMINATION for LLDNick Desaulniers2023-06-251-1/+2
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