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path: root/drivers/clk/actions
Commit message (Expand)AuthorAgeFilesLines
* clk: actions: remove redundant assignment after a mask operationColin Ian King2022-04-221-1/+1
* clk: actions: Make sentinel elements more obviousJonathan Neuschäfer2022-03-113-29/+31
* clk: actions: Terminate clk_div_table with sentinel elementJonathan Neuschäfer2022-03-112-1/+2
* clk/actions/owl-factor.c: remove superfluous headersMianhan Liu2021-11-021-1/+0
* clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea2021-06-271-1/+16
* clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea2021-06-271-8/+11
* clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea2021-06-271-15/+29
* clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea2021-06-271-4/+2
* clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea2021-06-271-6/+6
* clk: actions: Add Actions S500 SoC Reset Management Unit supportCristian Ciocaltea2020-07-211-0/+78
* clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoCCristian Ciocaltea2020-07-211-0/+9
* clk: actions: Fix h_clk for Actions S500 SoCCristian Ciocaltea2020-07-211-1/+1
*-. Merge branches 'clk-cdce-regulator', 'clk-bcm', 'clk-evict-parent-cache' and ...Stephen Boyd2019-09-191-4/+3
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| | * clk: actions: Fix factor clk struct member accessManivannan Sadhasivam2019-09-171-4/+3
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* / clk: actions: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
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* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
* clk: actions: Use the correct style for SPDX License IdentifierNishad Kamdar2019-05-019-9/+9
* clk: actions: Add clock driver for S500 SoCManivannan Sadhasivam2019-02-223-0/+531
* clk: actions: Add configurable PLL delayManivannan Sadhasivam2019-02-212-7/+25
* clk: actions: Add Actions Semi S900 SoC Reset Management Unit supportManivannan Sadhasivam2018-10-161-0/+82
* clk: actions: Add Actions Semi S700 SoC Reset Management Unit supportManivannan Sadhasivam2018-10-161-0/+51
* clk: actions: Add Actions Semi Owl SoCs Reset Management Unit supportManivannan Sadhasivam2018-10-165-0/+101
* clk: actions: Cache regmap info in private clock descriptorManivannan Sadhasivam2018-10-164-6/+8
* clk: actions: Add S700 SoC clock supportSaravanan Sekar2018-07-253-0/+613
* clk: actions: Add missing REGMAP_MMIO dependencySaravanan Sekar2018-07-251-0/+1
* clk: actions: Add S900 SoC clock supportManivannan Sadhasivam2018-04-063-0/+734
* clk: actions: Add pll clock supportManivannan Sadhasivam2018-04-063-0/+287
* clk: actions: Add composite clock supportManivannan Sadhasivam2018-04-063-0/+324
* clk: actions: Add fixed factor clock supportManivannan Sadhasivam2018-04-061-0/+28
* clk: actions: Add factor clock supportManivannan Sadhasivam2018-04-063-0/+306
* clk: actions: Add divider clock supportManivannan Sadhasivam2018-04-063-0/+170
* clk: actions: Add mux clock supportManivannan Sadhasivam2018-04-063-0/+122
* clk: actions: Add gate clock supportManivannan Sadhasivam2018-04-063-0/+151
* clk: actions: Add common clock driver supportManivannan Sadhasivam2018-04-064-0/+137
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 20:47:18 +0000