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path: root/drivers/clk/at91
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* clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea2021-10-261-1/+1
* clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea2021-10-261-10/+1
* clk: at91: clk-master: add notifier for dividerClaudiu Beznea2021-10-2613-82/+186
* clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea2021-10-264-29/+95
* clk: at91: clk-master: fix prescaler logicClaudiu Beznea2021-10-261-1/+1
* clk: at91: clk-master: mask mckr against layout->maskClaudiu Beznea2021-10-261-2/+5
* clk: at91: clk-master: check if div or pres is zeroClaudiu Beznea2021-10-261-2/+2
* clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea2021-10-261-2/+2
* clk: at91: pmc: add sama7g5 to the list of available pmcsClaudiu Beznea2021-10-261-2/+3
* clk: at91: clk-master: improve readability by using local variablesClaudiu Beznea2021-10-261-3/+3
* clk: at91: clk-master: add register definition for sama7g5's master clockClaudiu Beznea2021-10-261-27/+23
* clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea2021-10-261-0/+1
* clk: at91: pmc: execute suspend/resume only for backup modeClaudiu Beznea2021-10-261-0/+39
* clk: at91: re-factor clocks suspend/resumeClaudiu Beznea2021-10-2612-181/+558
* clk: at91: check pmc node status before registering syscore opsClément Léger2021-10-071-0/+5
*-. Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-rali...Stephen Boyd2021-09-011-7/+7
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| | * clk: at91: sama7g5: remove all kernel-doc & kernel-doc warningsRandy Dunlap2021-08-281-7/+7
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* / clk: at91: clk-generated: Limit the requested rate to our rangeCodrin Ciubotariu2021-08-281-0/+6
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* clk: at91: Trivial typo fixes in the file sama7g5.cBhaskar Chowdhury2021-03-131-3/+3
* clk: at91: Fix the declaration of the clocksTudor Ambarus2021-02-099-28/+28
* clk: at91: sam9x60: remove atmel,osc-bypass supportAlexandre Belloni2020-12-191-5/+1
* clk: at91: sama7g5: register cpu clockClaudiu Beznea2020-12-191-7/+6
* clk: at91: clk-master: re-factor master clockClaudiu Beznea2020-12-1914-146/+542
* clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea2020-12-191-14/+47
* clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea2020-12-191-1/+1
* clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea2020-12-191-29/+26
* clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea2020-12-194-41/+197
* clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev2020-12-191-2/+2
* clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2020-12-192-2/+2
* clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev2020-12-191-2/+4
* dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev2020-12-191-3/+3
* clk: at91: sama7g5: fix compilation errorClaudiu Beznea2020-12-191-2/+4
*-. Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom...Stephen Boyd2020-10-204-8/+12
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| | * clk: at91: sam9x60: support only two programmable clocksClaudiu Beznea2020-10-141-1/+1
| | * clk: at91: clk-sam9x60-pll: remove unused variableClaudiu Beznea2020-10-131-2/+1
| | * clk: at91: clk-main: update key before writing AT91_CKGR_MORClaudiu Beznea2020-10-131-3/+8
| | * clk: at91: remove the checking of parent_nameClaudiu Beznea2020-10-131-2/+2
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* / clk: at91: drop unused at91sam9g45_pcr_layoutKrzysztof Kozlowski2020-09-221-7/+0
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* clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea2020-07-242-0/+1060
* clk: at91: clk-utmi: add utmi support for sama7g5Claudiu Beznea2020-07-242-5/+102
* clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputsClaudiu Beznea2020-07-243-186/+433
* clk: at91: clk-programmable: add mux_table optionClaudiu Beznea2020-07-2413-17/+38
* clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea2020-07-249-16/+119
* clk: at91: clk-master: add master clock support for SAMA7G5Claudiu Beznea2020-07-242-5/+312
* clk: at91: clk-generated: add mux_table optionClaudiu Beznea2020-07-245-8/+16
* clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea2020-07-245-35/+37
* clk: at91: replace conditional operator with double logical notClaudiu Beznea2020-07-245-8/+8
* clk: at91: sckc: register slow_rc with accuracy optionClaudiu Beznea2020-07-241-2/+3
* clk: at91: sam9x60: fix main rc oscillator frequencyClaudiu Beznea2020-07-241-1/+1
* clk: at91: sam9x60-pll: use frac when setting frequencyClaudiu Beznea2020-07-241-4/+8