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path: root/drivers/clk/imx
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* clk: imx: use module_platform_driverMiles Chen2021-12-022-2/+2
* clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular compositesAlexander Stein2021-11-051-2/+2
* clk: imx: Make CLK_IMX8ULP select MXC_CLKFabio Estevam2021-10-061-0/+1
* clk: imx: imx6ul: Fix csi clk gate registerStefan Riedmueller2021-10-011-1/+6
* clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller2021-10-011-1/+1
* clk: imx: Fix the build break when clk-imx8ulp build as moduleJacky Bai2021-10-013-0/+3
* clk: imx: Add the pcc reset controller support on imx8ulpJacky Bai2021-09-302-3/+123
* clk: imx: Add clock driver for imx8ulpJacky Bai2021-09-303-0/+467
* clk: imx: Update the pfdv2 for 8ulp specific supportJacky Bai2021-09-303-13/+21
* clk: imx: disable the pfd when set pfdv2 clock rateJacky Bai2021-09-301-2/+11
* clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulpJacky Bai2021-09-301-1/+1
* clk: imx: disable i.mx7ulp composite clock during initializationAnson Huang2021-09-301-0/+14
* clk: imx: Update the compsite driver to support imx8ulpJacky Bai2021-09-302-3/+64
* clk: imx: Update the pllv4 to support imx8ulpJacky Bai2021-09-303-13/+34
* clk: imx: Rework imx_clk_hw_pll14xx wrapperAbel Vesa2021-09-301-7/+3
* clk: imx: Rework all imx_clk_hw_composite wrappersAbel Vesa2021-09-302-32/+36
* clk: imx: Rework all clk_hw_register_divider wrappersAbel Vesa2021-09-301-18/+11
* clk: imx: Rework all clk_hw_register_mux wrappersAbel Vesa2021-09-301-46/+22
* clk: imx: Rework all clk_hw_register_gate2 wrappersAbel Vesa2021-09-301-51/+26
* clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa2021-09-171-41/+23
* clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa2021-09-171-20/+6
* clk: imx: Remove unused helpersAbel Vesa2021-09-171-103/+0
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2021-09-027-21/+43
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| *-. Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-rali...Stephen Boyd2021-09-016-21/+42
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| | | * clk: imx8mn: Add M7 core clockMarek Vasut2021-08-241-0/+5
| | | * clk: imx8m: fix clock tree update of TF-A managed clocksAhmad Fatoum2021-08-245-12/+28
| | | * clk: imx: clk-divider-gate: Switch to clk_divider.determine_rateMartin Blumenstingl2021-08-241-5/+5
| | | * clk: imx8mn: use correct mux type for clkout pathLucas Stach2021-08-241-2/+2
| | | * clk: imx8mm: use correct mux type for clkout pathLucas Stach2021-08-241-2/+2
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| * / clk: fractional-divider: Hide clk_fractional_divider_ops from wide audienceAndy Shevchenko2021-08-121-0/+1
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* / clk: imx6q: fix uart earlycon unworkDong Aisheng2021-08-051-1/+1
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* clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach2021-06-141-38/+18
* clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg2021-06-141-12/+18
* clk: imx: scu: add parent save and restoreDong Aisheng2021-06-141-1/+28
* clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang2021-06-141-1/+8
* clk: imx: scu: Add A72 frequency scaling supportAnson Huang2021-06-141-1/+3
* clk: imx: scu: Add A53 frequency scaling supportAnson Huang2021-06-141-2/+2
* clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng2021-06-141-1/+1
* clk: imx: scu: detach pd if can't power upDong Aisheng2021-06-141-0/+1
* clk: imx: scu: bypass cpu clock save and restoreDong Aisheng2021-06-141-0/+10
* clk: imx: scu: add parallel port clock opsGuoniu.zhou2021-06-141-0/+8
* clk: imx: scu: add more scu clocksDong Aisheng2021-06-141-2/+150
* clk: imx: scu: add enet rgmii gpr clocksDong Aisheng2021-06-141-4/+18
* clk: imx8qm: add clock valid resource checkingDong Aisheng2021-06-144-1/+119
* clk: imx8qxp: add clock valid checking mechnismDong Aisheng2021-06-145-8/+137
* clk: imx: scu: add gpr clocks supportDong Aisheng2021-06-142-0/+215
* clk: imx: scu: remove legacy scu clock binding supportDong Aisheng2021-06-142-135/+81
* clk: imx: Remove the audio ipg clock from imx8mpJacky Bai2021-06-141-1/+0
* clk: imx: Reference preceded by freeJian Dong2021-04-042-0/+2
* clk: imx8mq: Correct the pcie1 selsRichard Zhu2021-04-041-2/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-02 20:50:14 +0000