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path: root/drivers/clk/ingenic/cgu.c
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* clk: ingenic: cgu: Switch to determine_rateMaxime Ripard2023-06-081-7/+8
* clk: ingenic: Add .set_rate_hook() for PLL clocksAidan MacDonald2022-10-271-0/+3
* clk: ingenic: Make PLL clock enable_bit and stable_bit optionalAidan MacDonald2022-10-271-1/+13
* clk: ingenic: Make PLL clock "od" field optionalAidan MacDonald2022-10-271-8/+17
* clk: ingenic: Allow specifying common clock flagsAidan MacDonald2022-05-181-1/+1
* clk: ingenic: Fix bugs with divided dividersPaul Cercueil2021-11-021-3/+3
* clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2021-06-271-13/+27
* clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil2021-06-271-2/+2
* clk: ingenic: Read bypass register only when there is onePaul Cercueil2021-06-271-8/+11
* clk: Support bypassing dividersPaul Cercueil2021-06-271-11/+22
* clk: ingenic: Fix divider calculation with div tablesPaul Cercueil2020-12-191-4/+10
* clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil2020-10-131-0/+2
* clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil2020-10-131-7/+7
* clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil2020-10-131-2/+7
* clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil2020-10-131-26/+29
* clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil2020-10-131-39/+15
* clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-281-3/+13
* clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-281-11/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-6/+35
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| * clk: ingenic: Add support for divider tablesPaul Cercueil2019-06-071-6/+35
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: ingenic: Remove set but not used variable 'enable'YueHaibing2019-02-261-2/+1
* clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil2019-02-221-5/+5
* clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil2018-06-011-0/+3
* clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil2018-06-011-2/+3
* clk: ingenic: Add code to enable/disable PLLsPaul Cercueil2018-01-181-15/+74
* clk: ingenic: support PLLs with no bypass bitPaul Cercueil2018-01-181-1/+2
* clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil2018-01-181-0/+2
* Update MIPS email addressesPaul Burton2017-11-031-1/+1
* clk: ingenic: Allow divider value to be dividedHarvey Hunt2016-05-121-1/+10
* clk: ingenic: Include clk.hStephen Boyd2015-07-201-0/+1
* clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton2015-06-211-0/+711