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path: root/drivers/clk/ingenic/cgu.h
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* clk: ingenic: Add .set_rate_hook() for PLL clocksAidan MacDonald2022-10-271-0/+4
* clk: ingenic: Make PLL clock enable_bit and stable_bit optionalAidan MacDonald2022-10-271-4/+6
* clk: ingenic: Make PLL clock "od" field optionalAidan MacDonald2022-10-271-1/+2
* clk: ingenic: Allow specifying common clock flagsAidan MacDonald2022-05-181-0/+3
* clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2021-06-271-0/+3
* clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil2021-06-271-4/+3
* clk: Support bypassing dividersPaul Cercueil2021-06-271-0/+2
* clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-281-0/+4
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-0/+4
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| * clk: ingenic: Add missing header in cgu.hPaul Cercueil2019-06-251-0/+1
| * clk: ingenic: Add support for divider tablesPaul Cercueil2019-06-071-0/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
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* clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil2019-02-221-1/+1
* docs: Fix some broken referencesMauro Carvalho Chehab2018-06-151-1/+1
* clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil2018-06-011-0/+2
* clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil2018-06-011-0/+2
* clk: ingenic: support PLLs with no bypass bitPaul Cercueil2018-01-181-0/+2
* clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil2018-01-181-1/+1
* Update MIPS email addressesPaul Burton2017-11-031-1/+1
* clk: ingenic: Allow divider value to be dividedHarvey Hunt2016-05-121-1/+5
* clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton2015-06-211-0/+223