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path: root/drivers/clk/mediatek
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* Merge branch 'clk-rate-range' into clk-nextStephen Boyd2022-10-141-0/+10
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| * clk: mediatek: clk-mux: Add .determine_rate() callbackAngeloGioacchino Del Regno2022-10-141-0/+10
* | clk: mediatek: add driver for MT8365 SoCFabien Parent2022-09-309-0/+1614
* | clk: mediatek: Export required common code symbolsMarkus Schneider-Pargmann2022-09-301-0/+2
* | clk: mediatek: Provide mtk_devm_alloc_clk_dataMarkus Schneider-Pargmann2022-09-302-5/+30
* | clk: mediatek: mt8192: deduplicate parent clock listsChen-Yu Tsai2022-09-291-181/+25
* | clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()Chen-Yu Tsai2022-09-291-5/+5
* | clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanupChen-Yu Tsai2022-09-291-1/+1
* | clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_selAngeloGioacchino Del Regno2022-09-291-0/+28
* | clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parentAngeloGioacchino Del Regno2022-09-291-2/+4
* | clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parentsAngeloGioacchino Del Regno2022-09-291-3/+6
* | clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifierAngeloGioacchino Del Regno2022-09-291-0/+20
* | clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic muxAngeloGioacchino Del Regno2022-09-291-12/+7
* | clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changesAngeloGioacchino Del Regno2022-09-291-2/+4
* | clk: mediatek: mt8183: Add clk mux notifier for MFG muxChen-Yu Tsai2022-09-291-0/+28
* | clk: mediatek: mux: add clk notifier functionsChen-Yu Tsai2022-09-292-0/+53
* | clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parentChen-Yu Tsai2022-09-291-3/+3
* | clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probeYassine Oudjana2022-09-261-1/+2
* | clk: mediatek: gate: Export mtk_clk_register_gates_with_devYassine Oudjana2022-09-261-0/+1
* | clk: mediatek: add VDOSYS1 clockPablo Sun2022-09-261-0/+11
* | clk: mediatek: mt8192: add mtk_clk_simple_removeMiles Chen2022-09-2610-0/+10
* | clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driverMiles Chen2022-09-269-137/+108
* | clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driverMiles Chen2022-09-263-69/+39
* | clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driverMiles Chen2022-09-267-111/+90
* | clk: mediatek: mt6765: use mtk_clk_simple_probe to simplify driverMiles Chen2022-09-266-129/+72
* | clk: mediatek: mt2712: use mtk_clk_simple_probe to simplify driverMiles Chen2022-09-266-132/+72
* | clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driverMiles Chen2022-09-263-69/+39
* | clk: mediatek: Add MediaTek Helio X10 MT6795 clock driversAngeloGioacchino Del Regno2022-09-2610-0/+1408
* | clk: mediatek: clk-apmixed: Add helper function to unregister ref2usb_txAngeloGioacchino Del Regno2022-09-262-0/+10
* | clk: mediatek: Export required symbols to compile clk drivers as moduleAngeloGioacchino Del Regno2022-09-264-0/+6
* | clk: mediatek: clk-apmixed: Remove unneeded __init annotationAngeloGioacchino Del Regno2022-09-261-1/+1
* | clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHYAngeloGioacchino Del Regno2022-08-311-0/+1
* | clk: mediatek: mt8195-infra_ao: Set pwrmcu clocks as criticalAngeloGioacchino Del Regno2022-08-311-3/+10
* | clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1AngeloGioacchino Del Regno2022-08-311-0/+2
* | clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parentAngeloGioacchino Del Regno2022-08-311-1/+5
* | clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parentAngeloGioacchino Del Regno2022-08-311-1/+6
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* clk: mediatek: reset: Add infra_ao reset support for MT8186Rex-BC Chen2022-06-151-0/+23
* clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195Rex-BC Chen2022-06-154-6/+60
* clk: mediatek: reset: Add reset support for simple probeRex-BC Chen2022-06-152-0/+8
* clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen2022-06-1513-16/+86
* clk: mediatek: reset: Change return type for clock reset register functionRex-BC Chen2022-06-152-8/+13
* clk: mediatek: reset: Support inuput argument index modeRex-BC Chen2022-06-152-1/+25
* clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen2022-06-1515-43/+85
* clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen2022-06-1515-40/+186
* clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen2022-06-1515-46/+61
* clk: mediatek: reset: Extract common drivers to update functionRex-BC Chen2022-06-151-16/+22
* clk: mediatek: reset: Refine and reorder functions in reset.cRex-BC Chen2022-06-151-32/+36
* clk: mediatek: reset: Fix written reset bit offsetRex-BC Chen2022-06-151-2/+2
* clk: mediatek: reset: Add reset.hRex-BC Chen2022-06-153-14/+27
* clk: mediatek: Delete MT8192 msdc gateMatthias Brugger2022-06-091-21/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 04:29:27 +0000