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path: root/drivers/clk/mediatek
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* clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.cRan Jianping2021-11-021-2/+0
* clk: mediatek: Export clk_ops structures to modulesStephen Boyd2021-09-141-0/+2
* clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen2021-09-1410-17/+35
* clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen2021-09-148-1/+33
* clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen2021-09-142-1/+94
* clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen2021-09-142-1/+69
* clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen2021-09-142-1/+145
* clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen2021-09-142-1/+109
* clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen2021-09-142-1/+111
* clk: mediatek: Add MT8195 vencsys clock supportChun-Jie Chen2021-09-142-1/+71
* clk: mediatek: Add MT8195 vdosys1 clock supportChun-Jie Chen2021-09-142-1/+141
* clk: mediatek: Add MT8195 vdosys0 clock supportChun-Jie Chen2021-09-142-1/+124
* clk: mediatek: Add MT8195 vdecsys clock supportChun-Jie Chen2021-09-142-1/+106
* clk: mediatek: Add MT8195 scp adsp clock supportChun-Jie Chen2021-09-142-1/+48
* clk: mediatek: Add MT8195 mfgcfg clock supportChun-Jie Chen2021-09-142-1/+48
* clk: mediatek: Add MT8195 ipesys clock supportChun-Jie Chen2021-09-142-1/+53
* clk: mediatek: Add MT8195 imgsys clock supportChun-Jie Chen2021-09-142-1/+97
* clk: mediatek: Add MT8195 ccusys clock supportChun-Jie Chen2021-09-142-1/+51
* clk: mediatek: Add MT8195 camsys clock supportChun-Jie Chen2021-09-142-1/+144
* clk: mediatek: Add MT8195 infrastructure clock supportChun-Jie Chen2021-09-142-1/+207
* clk: mediatek: Add MT8195 peripheral clock supportChun-Jie Chen2021-09-142-1/+64
* clk: mediatek: Add MT8195 topckgen clock supportChun-Jie Chen2021-09-142-1/+1274
* clk: mediatek: Add MT8195 apmixedsys clock supportChun-Jie Chen2021-09-143-0/+154
* clk: mediatek: Fix resource leak in mtk_clk_simple_probeChun-Jie Chen2021-09-141-2/+10
* clk: mediatek: Add API for clock resource recycleChun-Jie Chen2021-09-142-0/+10
* clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen2021-09-141-1/+1
* clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167Miles Chen2021-07-271-15/+10
* clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen2021-07-273-0/+60
* clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen2021-07-273-0/+101
* clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen2021-07-273-0/+57
* clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen2021-07-273-0/+92
* clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen2021-07-273-0/+115
* clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen2021-07-273-0/+57
* clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen2021-07-273-0/+89
* clk: mediatek: Add MT8192 ipesys clock supportChun-Jie Chen2021-07-273-0/+64
* clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen2021-07-273-0/+126
* clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen2021-07-273-0/+77
* clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen2021-07-273-0/+114
* clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen2021-07-273-0/+125
* clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen2021-07-275-4/+1358
* clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providersChun-Jie Chen2021-07-272-0/+31
* clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2021-07-272-14/+21
* clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen2021-07-271-4/+16
* clk: mediatek: Get regmap without syscon compatible checkChun-Jie Chen2021-07-274-4/+4
* clk: mediatek: mux: Update parent at enable timeLaurent Pinchart2021-02-092-3/+30
* clk: mediatek: mux: Drop unused clock opsLaurent Pinchart2021-02-092-70/+4
* clk: mediatek: Select all the MT8183 clocks by defaultEnric Balletbo i Serra2021-02-081-0/+11
* clk: mediatek: Make mtk_clk_register_mux() a static functionWeiyi Lu2020-12-172-5/+1
*-. Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk...Stephen Boyd2020-10-2012-14/+1511
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| | * clk: mediatek: Add MT8167 clock supportFabien Parent2020-10-138-0/+1505
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