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path: root/drivers/clk/meson/meson8b.c
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* clk: meson: Hold reference returned by of_get_parent()Liang He2022-08-191-1/+4
* clk: cleanup commentsTom Rix2022-03-111-1/+1
* clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl2021-09-231-38/+38
* clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl2021-09-231-4/+36
* clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl2021-09-231-0/+22
* clk: meson: meson8b: Add the vid_pll_lvds_en gate clockMartin Blumenstingl2021-09-231-1/+22
* clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_selMartin Blumenstingl2021-09-231-2/+2
* clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl2021-01-041-40/+5
* clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl2020-07-091-5/+25
* clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl2020-07-091-5/+25
* clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl2020-06-241-7/+0
* clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2020-05-021-0/+9
* clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl2020-04-291-3/+11
* clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl2020-04-291-5/+5
* clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl2020-04-291-23/+56
* clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl2020-04-291-1/+1
* clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl2020-04-141-3/+3
* clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl2020-02-211-8/+13
* clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl2020-01-071-4/+7
* clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl2019-12-111-1/+1
* clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl2019-12-111-3/+9
* clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl2019-12-111-34/+44
* clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl2019-12-111-13/+8
* clk: meson: clk-regmap: migrate to new parent description methodAlexandre Mergnat2019-07-291-0/+3
* clk: meson: meson8b: migrate to the new parent description methodAlexandre Mergnat2019-07-291-211/+496
* clk: meson: meson8b: add the cts_i958 clockMartin Blumenstingl2019-06-111-0/+24
* clk: meson: meson8b: add the cts_mclk_i958 clocksMartin Blumenstingl2019-06-111-0/+65
* clk: meson: meson8b: add the cts_amclk clocksMartin Blumenstingl2019-06-111-0/+65
* clk: meson: meson8b: fix a typo in the VPU parent names array variableMartin Blumenstingl2019-05-201-5/+5
* clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl2019-04-011-0/+312
* clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl2019-04-011-0/+167
* clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl2019-04-011-0/+62
* clk: meson: meson8b: use a separate clock table for Meson8m2Martin Blumenstingl2019-04-011-1/+192
* clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl2019-02-131-13/+13
* clk: meson: rework and clean drivers dependenciesJerome Brunet2019-02-021-1/+2
* clk: meson: meson8b: add the GPU clock treeMartin Blumenstingl2019-01-071-0/+146
* clk: meson: meson8b: use a separate clock table for Meson8Martin Blumenstingl2019-01-071-6/+197
* clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2018-12-031-8/+731
* clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2018-12-031-0/+5
* clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl2018-12-031-1/+1
* clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2018-11-231-0/+244
* clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2018-11-231-10/+10
* clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl2018-11-231-6/+6
* clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl2018-11-231-0/+63
* clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl2018-11-231-0/+5
* clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2018-11-231-1/+2
* clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2018-11-231-2/+9
* clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2018-11-231-1/+1
* clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2018-11-231-7/+8
* clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl2018-11-231-9/+15
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