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path: root/drivers/clk/meson
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| | | * dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong2023-08-081-15/+0
| | | * dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong2023-08-081-63/+0
| | | * dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong2023-08-081-108/+0
| | | * dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong2023-08-081-17/+0
| | | * dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong2023-08-081-140/+0
| | | * dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong2023-08-081-58/+0
| | | * dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong2023-08-081-76/+0
| | | * clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-083-428/+424
| | | * clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-083-658/+660
| | | * clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-085-180/+183
| | | * clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-089-73/+68
| | | * clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-089-1323/+1312
| | | * clk: meson: introduce meson-clkc-utilsNeil Armstrong2023-08-084-0/+48
| | |/
| * / clk: Explicitly include correct DT includesRob Herring2023-07-198-8/+8
| |/
* / clk: meson: change usleep_range() to udelay() for atomic contextDmitry Rokosov2023-07-111-2/+2
|/
* clk: meson: pll: remove unneeded semicolonJiapeng Chong2023-06-151-1/+1
* clk: meson: a1: Staticize rtc clkStephen Boyd2023-06-121-1/+1
* clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov2023-05-304-0/+2367
* clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov2023-05-304-0/+414
* clk: meson: introduce new pll power-on sequence for A1 SoC familyDmitry Rokosov2023-05-302-0/+25
* clk: meson: make pll rst bit as optionalDmitry Rokosov2023-05-301-7/+17
* clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-5/+4
* clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-5/+6
* clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-8/+13
* clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl2023-01-131-7/+13
*-. Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ...Stephen Boyd2022-12-121-8/+12
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| | * clk: meson: pll: add pcie lock retry workaroundHeiner Kallweit2022-11-081-4/+8
| | * clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()Heiner Kallweit2022-11-081-4/+4
| |/
* / clk: Remove a useless includeChristophe JAILLET2022-11-221-1/+0
|/
* clk: meson: Hold reference returned by of_get_parent()Liang He2022-08-193-3/+12
* clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König2022-06-151-32/+4
* clk: cleanup commentsTom Rix2022-03-111-1/+1
* clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl2021-11-301-3/+41
* clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl2021-09-231-38/+38
* clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl2021-09-232-5/+48
* clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl2021-09-231-0/+22
* clk: meson: meson8b: Add the vid_pll_lvds_en gate clockMartin Blumenstingl2021-09-232-2/+24
* clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_selMartin Blumenstingl2021-09-231-2/+2
* clk: meson: meson8b: Export the video clocksMartin Blumenstingl2021-09-231-11/+1
* clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl2021-06-301-10/+9
* clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie2021-06-091-0/+6
* clk: meson: axg-audio: improve deferral handlingJerome Brunet2021-05-241-3/+2
* clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet2021-05-201-1/+1
* clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl2021-05-191-11/+15
* clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel2021-02-092-4/+0
* clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl2021-01-041-40/+5
* clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl2021-01-041-2/+3
* clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl2021-01-041-1/+2
* clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl2021-01-041-1/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-12-2111-61/+1004
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