| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | clk: renesas: r8a77965: Remove superfluous semicolon | Geert Uytterhoeven | 2019-11-01 | 1 | -1/+1 |
| * | clk: renesas: r8a77965: Add CMM clocks | Jacopo Mondi | 2019-06-18 | 1 | -0/+3 |
| * | clk: renesas: r8a779{5|6|65}: Add TPU clock | Cao Van Dong | 2019-05-21 | 1 | -0/+1 |
| * | clk: renesas: rcar-gen3: Rename DRIF clocks | Takeshi Kihara | 2019-04-02 | 1 | -8/+9 |
| * | clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC | Takeshi Kihara | 2019-04-02 | 1 | -2/+2 |
| * | clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC | Takeshi Kihara | 2019-04-02 | 1 | -2/+2 |
| * | clk: renesas: rcar-gen3: Correct parent clock of HS-USB | Kazuya Mizuguchi | 2019-04-02 | 1 | -1/+1 |
| * | clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI | Kazuya Mizuguchi | 2019-04-02 | 1 | -2/+2 |
| * | clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset | Simon Horman | 2019-04-02 | 1 | -1/+1 |
| * | clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor | Takeshi Kihara | 2019-04-02 | 1 | -1/+1 |
| * | clk: renesas: r8a77965: Add CPEX clock | Geert Uytterhoeven | 2018-12-04 | 1 | -0/+1 |
| * | clk: renesas: r8a77965: Add FDP clock | Hoan Nguyen An | 2018-08-28 | 1 | -0/+1 |
| * | clk: renesas: r8a77965: Add SATA clock | Takeshi Kihara | 2018-08-27 | 1 | -0/+1 |
| * | clk: renesas: r8a77965: Add OSC EXTAL predivider configuration | Geert Uytterhoeven | 2018-08-27 | 1 | -33/+33 |
| * | clk: renesas: rcar-gen3: Rename rint to .r | Geert Uytterhoeven | 2018-08-27 | 1 | -1/+2 |
| * | clk: renesas: r8a77965: Add MSIOF controller clocks | Takeshi Kihara | 2018-04-16 | 1 | -0/+4 |
| * | clk: renesas: r8a77965: Replace DU2 clock | Jacopo Mondi | 2018-03-13 | 1 | -1/+1 |
| * | clk: renesas: cpg-mssr: Add support for R-Car M3-N | Jacopo Mondi | 2018-02-26 | 1 | -0/+334 |
