summaryrefslogtreecommitdiffstats
path: root/drivers/clk/renesas/r8a77980-cpg-mssr.c
Commit message (Collapse)AuthorAgeFilesLines
* clk: renesas: r8a77980: Add I2C5 clockNikita Yushchenko2023-03-301-0/+1
| | | | | | | | | The MSSR clock definition for I2C5 was missing. Add it. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230328033902.830269-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Add Z2 clockGeert Uytterhoeven2023-03-101-0/+1
| | | | | | | | Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3H, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/aad9eaa57acf65cbe43e4d374066a72d760d54d8.1676560357.git.geert+renesas@glider.be
* clk: renesas: r8a77980: Add VIN clocksNiklas Söderlund2023-03-061-0/+16
| | | | | | | | | | Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V3H (R8A77980) SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230211153026.3898491-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Move RPC core clocksGeert Uytterhoeven2022-04-131-5/+5
| | | | | | | | | | | | | The RPC and RPCD2 core clocks were added to the sections for internal core clocks, while they are core clock outputs, visible from DT. Move them to the correct sections. Rename the ".rpc" clock on R-Car S4 to "rpc". Fixup nearby whitespace to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
* clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang2021-11-191-1/+2
| | | | | | | | | Currently a pass-through clock but we will make it a real divider clock in the next patches. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht2020-06-221-1/+1
| | | | | | | | | | | Ensures RWDT remains alert throughout the boot process if enabled. This patch applies the change to the following SoCs: r8a77950, r8a77951, r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Fix RPC-IF module clock's parentSergei Shtylyov2019-04-021-1/+1
| | | | | | | | | Testing has shown that the RPC-IF module clock's parent is the RPCD2 clock, not the RPC one -- the RPC-IF register reads stall otherwise... Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Add RPC clocksSergei Shtylyov2019-02-051-0/+8
| | | | | | | | | Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Add CMT clocksSergei Shtylyov2018-09-031-0/+4
| | | | | | | | | | Now that RCLK has been added by Geert, we can add the CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a77980: Add RCLK for watchdog timerGeert Uytterhoeven2018-08-271-0/+4
| | | | | | | | On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip Oscillator using mode pin MD19. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a77980: Add OSC predivider configuration and clockGeert Uytterhoeven2018-08-271-11/+13
| | | | | | | | | | | | R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC clock. Hence augment the configuration structure with all documented predivider values. Add the OSC clock using the configured predivider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a77980: Correct parent clock of PCIEC0Geert Uytterhoeven2018-04-161-1/+1
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of December 22, 2017, the parent clock of the PCIe module clock on R-Car V3H is S2D2. Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: cpg-mssr: add R8A77980 supportSergei Shtylyov2018-02-201-0/+227
Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 20:30:18 +0000