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path: root/drivers/clk/renesas/r8a77995-cpg-mssr.c
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* clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto2023-08-151-0/+1
* clk: renesas: r8a77995: Fix VIN parent clockGeert Uytterhoeven2023-03-061-1/+1
* clk: renesas: Move RPC core clocksGeert Uytterhoeven2022-04-131-6/+4
* clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven2022-04-111-0/+9
* clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko2022-01-241-0/+1
* clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang2021-11-191-1/+2
* clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto2021-05-271-0/+1
* clk: renesas: r8a77995: Add TMU clocksNiklas Söderlund2020-12-281-0/+5
* clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht2020-06-221-1/+1
* clk: renesas: rcar-gen3: Add CCREE clocksGeert Uytterhoeven2020-02-101-0/+2
* clk: renesas: r8a77995: Add CMM clocksJacopo Mondi2019-06-181-0/+2
* clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara2019-04-021-1/+1
* clk: renesas: r8a77995: Simplify PLL3 multiplier/dividerGeert Uytterhoeven2018-12-041-2/+2
* clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven2018-12-041-1/+2
* clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven2018-12-041-1/+0
* clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocksGeert Uytterhoeven2018-12-041-3/+0
* clk: renesas: r8a77995: Correct parent clock of DUGeert Uytterhoeven2018-12-041-2/+2
* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-181-2/+10
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| * clk: renesas: r8a77995: Correct RCLK handlingGeert Uytterhoeven2018-08-271-2/+10
* | clk: renesas: use SPDX identifier for Renesas driversWolfram Sang2018-08-301-4/+1
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* clk: renesas: r8a77995: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+1
* clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven2017-08-161-0/+236