summaryrefslogtreecommitdiffstats
path: root/drivers/clk/renesas/r9a06g032-clocks.c
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
* clk: renesas: r9a06g032: Improve clock tablesRalph Siemsen2023-03-101-153/+407
* clk: renesas: r9a06g032: Document structsRalph Siemsen2023-03-101-1/+49
* clk: renesas: r9a06g032: Drop unused fieldsRalph Siemsen2023-03-101-5/+10
* clk: renesas: r9a06g032: Improve readabilityRalph Siemsen2023-03-101-41/+80
* soc: renesas: r9a06g032-sysctrl: Handle h2mode setting based on USBF presenceHerve Codina2023-01-171-0/+28
* clk: renesas: r9a06g032: Repair grave increment errorMarek Vasut2022-11-011-2/+1
* clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen2022-06-061-4/+4
* clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen2022-06-061-13/+11
* Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2022-05-291-1/+39
|\
| * clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal2022-05-191-0/+5
| * clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal2022-05-191-1/+34
* | clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal2022-04-281-1/+1
|/
* clk: renesas: r9a06g032: Switch to .determine_rate()Geert Uytterhoeven2021-05-111-12/+13
* clk: renesas: Zero init clk_init_dataGeert Uytterhoeven2021-03-301-4/+4
* clk: renesas: Couple of spelling fixesBhaskar Chowdhury2021-03-241-2/+2
* clk: renesas: r9a06g032: Drop __packed for portabilityGeert Uytterhoeven2020-12-071-1/+1
* clk: renesas: r9a06g032: Fix some typo in commentsChristophe JAILLET2020-04-141-3/+3
* clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domainGeert Uytterhoeven2019-08-231-1/+2
* clk: renesas: r9a06g032: Add clock domain supportGareth Williams2019-06-041-69/+158
* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-151-0/+1
* clk: renesas: r9a06g032: Add missing PCI USB clockGareth Williams2019-04-021-0/+1
* clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd2018-12-101-4/+4
* clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy2018-09-111-1/+2
* clk: renesas: Renesas R9A06G032 clock driverMichel Pollet2018-06-251-0/+893