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path: root/drivers/clk/renesas/r9a07g043-cpg.c
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* clk: renesas: r9a07g043: Drop WDT2 clock and reset entryLad Prabhakar2022-10-261-5/+0
* clk: renesas: r9a07g043: Add support for RZ/Five SoCLad Prabhakar2022-07-051-0/+32
* clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-051-0/+2
* clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy2022-05-051-12/+6
* clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy2022-05-051-2/+1
* clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy2022-05-051-6/+4
* clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das2022-05-051-0/+6
* clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das2022-05-051-0/+6
* clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das2022-05-051-0/+9
* clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das2022-05-051-0/+18
* clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das2022-04-281-0/+10
* clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das2022-04-281-0/+9
* clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das2022-04-281-0/+5
* clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das2022-04-281-0/+12
* clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das2022-04-281-0/+20
* clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das2022-04-281-0/+12
* clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das2022-04-131-0/+35
* clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das2022-04-131-0/+10
* clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das2022-04-131-0/+13
* clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das2022-04-131-0/+5
* clk: renesas: Add support for RZ/G2UL SoCBiju Das2022-04-131-0/+157