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path: root/drivers/clk/renesas/r9a07g044-cpg.c
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: r9a07g044: Drop WDT2 clock and reset entryLad Prabhakar2022-10-261-6/+1
* clk: renesas: r9a07g044: Add MTU3a clock and reset entryBiju Das2022-10-171-1/+4
* clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_infoBiju Das2022-08-221-0/+2
* clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das2022-06-061-1/+13
* clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das2022-06-061-1/+4
* clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-051-0/+4
* clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy2022-05-051-15/+8
* clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy2022-05-051-4/+2
* clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy2022-05-051-9/+6
* clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven2022-05-051-1/+1
* clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das2022-05-051-1/+16
* clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das2022-05-051-1/+8
* clk: renesas: r9a07g044: Add M4 Clock supportBiju Das2022-05-051-1/+18
* clk: renesas: r9a07g044: Add M3 Clock supportBiju Das2022-05-051-1/+4
* clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das2022-05-051-1/+4
* clk: renesas: r9a07g044: Add M1 clock supportBiju Das2022-05-051-1/+10
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-101-190/+236
* clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar2022-01-241-2/+2
* clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das2021-12-081-0/+9
* clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das2021-12-081-0/+6
* clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das2021-12-081-2/+2
* clk: renesas: r9a07g044: Add TSU clock and reset entryBiju Das2021-11-261-0/+3
* clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar2021-11-191-0/+9
* clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIVBiju Das2021-11-191-1/+10
* clk: renesas: r9a07g044: Add OSTM clock and reset entriesBiju Das2021-11-151-0/+9
* clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macrosBiju Das2021-11-151-6/+6
* clk: renesas: r9a07g044: Add WDT clock and reset entriesBiju Das2021-11-151-0/+15
* clk: renesas: r9a07g044: Add clock and reset entry for SCI1Lad Prabhakar2021-11-151-0/+3
* clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das2021-10-081-0/+36
* clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar2021-10-081-0/+18
* clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das2021-09-241-0/+10
* clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das2021-09-241-1/+18
* clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das2021-09-241-0/+2
* clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar2021-07-261-1/+2
* clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar2021-07-191-0/+6
* clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar2021-07-191-0/+4
* clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven2021-07-191-1/+1
* clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar2021-07-191-0/+5
* clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das2021-07-191-0/+20
* clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das2021-07-191-0/+12
* clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das2021-07-191-0/+8
* clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das2021-07-191-0/+12
* dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das2021-07-121-26/+36
* clk: renesas: r9a07g044: Add P2 Clock supportBiju Das2021-07-121-0/+4
* clk: renesas: r9a07g044: Fix P1 ClockBiju Das2021-07-121-3/+3
* clk: renesas: r9a07g044: Rename divider tableBiju Das2021-07-121-3/+4
* clk: renesas: Add support for R9A07G044 SoCLad Prabhakar2021-06-101-0/+127
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 11:28:41 +0000