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linux-rolling-lts
linux-rolling-stable
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path:
root
/
drivers
/
clk
/
renesas
/
r9a07g044-cpg.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
clk: renesas: r9a07g044: Add clock and reset entries for CRU
Lad Prabhakar
2023-01-12
1
-1
/
+25
*
clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
Lad Prabhakar
2022-10-26
1
-6
/
+1
*
clk: renesas: r9a07g044: Add MTU3a clock and reset entry
Biju Das
2022-10-17
1
-1
/
+4
*
clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info
Biju Das
2022-08-22
1
-0
/
+2
*
clk: renesas: r9a07g044: Add POEG clock and reset entries
Biju Das
2022-06-06
1
-1
/
+13
*
clk: renesas: r9a07g044: Add GPT clock and reset entry
Biju Das
2022-06-06
1
-1
/
+4
*
clk: renesas: rzg2l: Make use of CLK_MON registers optional
Phil Edworthy
2022-05-05
1
-0
/
+4
*
clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
Phil Edworthy
2022-05-05
1
-15
/
+8
*
clk: renesas: rzg2l: Add read only versions of the clk macros
Phil Edworthy
2022-05-05
1
-4
/
+2
*
clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
Phil Edworthy
2022-05-05
1
-9
/
+6
*
clk: renesas: r9a07g044: Fix OSTM1 module clock name
Geert Uytterhoeven
2022-05-05
1
-1
/
+1
*
clk: renesas: r9a07g044: Add DSI clock and reset entries
Biju Das
2022-05-05
1
-1
/
+16
*
clk: renesas: r9a07g044: Add LCDC clock and reset entries
Biju Das
2022-05-05
1
-1
/
+8
*
clk: renesas: r9a07g044: Add M4 Clock support
Biju Das
2022-05-05
1
-1
/
+18
*
clk: renesas: r9a07g044: Add M3 Clock support
Biju Das
2022-05-05
1
-1
/
+4
*
clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
Biju Das
2022-05-05
1
-1
/
+4
*
clk: renesas: r9a07g044: Add M1 clock support
Biju Das
2022-05-05
1
-1
/
+10
*
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
Biju Das
2022-02-10
1
-190
/
+236
*
clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
Lad Prabhakar
2022-01-24
1
-2
/
+2
*
clk: renesas: r9a07g044: Add GPU clock and reset entries
Biju Das
2021-12-08
1
-0
/
+9
*
clk: renesas: r9a07g044: Add mux and divider for G clock
Biju Das
2021-12-08
1
-0
/
+6
*
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
Biju Das
2021-12-08
1
-2
/
+2
*
clk: renesas: r9a07g044: Add TSU clock and reset entry
Biju Das
2021-11-26
1
-0
/
+3
*
clk: renesas: r9a07g044: Add RSPI clock and reset entries
Lad Prabhakar
2021-11-19
1
-0
/
+9
*
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
Biju Das
2021-11-19
1
-1
/
+10
*
clk: renesas: r9a07g044: Add OSTM clock and reset entries
Biju Das
2021-11-15
1
-0
/
+9
*
clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
Biju Das
2021-11-15
1
-6
/
+6
*
clk: renesas: r9a07g044: Add WDT clock and reset entries
Biju Das
2021-11-15
1
-0
/
+15
*
clk: renesas: r9a07g044: Add clock and reset entry for SCI1
Lad Prabhakar
2021-11-15
1
-0
/
+3
*
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Biju Das
2021-10-08
1
-0
/
+36
*
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...
Lad Prabhakar
2021-10-08
1
-0
/
+18
*
clk: renesas: r9a07g044: Add GbEthernet clock/reset
Biju Das
2021-09-24
1
-0
/
+10
*
clk: renesas: r9a07g044: Add ethernet clock sources
Biju Das
2021-09-24
1
-1
/
+18
*
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
Biju Das
2021-09-24
1
-0
/
+2
*
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
Lad Prabhakar
2021-07-26
1
-1
/
+2
*
clk: renesas: r9a07g044: Add clock and reset entries for ADC
Lad Prabhakar
2021-07-19
1
-0
/
+6
*
clk: renesas: r9a07g044: Add clock and reset entries for CANFD
Lad Prabhakar
2021-07-19
1
-0
/
+4
*
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
Geert Uytterhoeven
2021-07-19
1
-1
/
+1
*
clk: renesas: r9a07g044: Add GPIO clock and reset entries
Lad Prabhakar
2021-07-19
1
-0
/
+5
*
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
Biju Das
2021-07-19
1
-0
/
+20
*
clk: renesas: r9a07g044: Add USB clocks/resets
Biju Das
2021-07-19
1
-0
/
+12
*
clk: renesas: r9a07g044: Add DMAC clocks/resets
Biju Das
2021-07-19
1
-0
/
+8
*
clk: renesas: r9a07g044: Add I2C clocks/resets
Biju Das
2021-07-19
1
-0
/
+12
*
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions
Biju Das
2021-07-12
1
-26
/
+36
*
clk: renesas: r9a07g044: Add P2 Clock support
Biju Das
2021-07-12
1
-0
/
+4
*
clk: renesas: r9a07g044: Fix P1 Clock
Biju Das
2021-07-12
1
-3
/
+3
*
clk: renesas: r9a07g044: Rename divider table
Biju Das
2021-07-12
1
-3
/
+4
*
clk: renesas: Add support for R9A07G044 SoC
Lad Prabhakar
2021-06-10
1
-0
/
+127