Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | clk: renesas: r9a09g011: Add USB clock and reset entries | Biju Das | 2022-12-27 | 1 | -0/+21 |
* | clk: renesas: r9a09g011: Add TIM clock and reset entries | Biju Das | 2022-12-27 | 1 | -0/+22 |
* | clk: renesas: r9a09g011: Add PWM clock and reset entries | Biju Das | 2022-12-26 | 1 | -0/+10 |
* | clk: renesas: r9a09g011: Add IIC clock and reset entries | Phil Edworthy | 2022-08-29 | 1 | -0/+4 |
* | clk: renesas: r9a09g011: Add WDT clock and reset entries | Phil Edworthy | 2022-06-06 | 1 | -0/+3 |
* | clk: renesas: r9a09g011: Add PFC clock and reset entries | Phil Edworthy | 2022-06-06 | 1 | -0/+2 |
* | clk: renesas: r9a09g011: Add eth clock and reset entries | Phil Edworthy | 2022-05-06 | 1 | -5/+9 |
* | clk: renesas: Add RZ/V2M support using the rzg2l driver | Phil Edworthy | 2022-05-06 | 1 | -0/+168 |