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path: root/drivers/clk/renesas/rzg2l-cpg.c
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea2023-12-131-15/+44
* clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()Claudiu Beznea2023-11-271-23/+15
* clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea2023-10-121-1/+1
* clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea2023-10-101-0/+6
* clk: renesas: rzg2l: Add divider clock for RZ/G3SClaudiu Beznea2023-10-101-0/+186
* clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea2023-10-101-42/+108
* clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea2023-10-051-18/+34
* clk: renesas: rzg2l: Add support for RZ/G3S PLLClaudiu Beznea2023-10-051-4/+45
* clk: renesas: rzg2l: Remove critical areaClaudiu Beznea2023-10-051-4/+1
* clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea2023-10-051-6/+6
* clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea2023-10-051-7/+1
* clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea2023-10-051-10/+13
* clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea2023-10-051-7/+10
* clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea2023-09-181-5/+5
* clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea2023-09-181-3/+2
* clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea2023-09-181-1/+1
*-. Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...Stephen Boyd2023-08-301-9/+2
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| | * clk: Explicitly include correct DT includesRob Herring2023-07-191-2/+1
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| * clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET2023-07-111-7/+1
|/
* clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-11/+5
* clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das2023-05-231-4/+2
* clk: renesas: remove MODULE_LICENSE in non-modulesNick Alcock2023-04-131-1/+0
* clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PMLad Prabhakar2022-10-281-15/+24
* clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldocLad Prabhakar2022-10-261-1/+1
* clk: renesas: rzg2l: Fix typo in function nameLad Prabhakar2022-10-171-3/+3
* clk: renesas: rzg2l: Support sd clk mux round operationBiju Das2022-10-171-1/+1
* clk: renesas: rzg2l: Fix reset status functionBiju Das2022-06-071-1/+1
* clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-061-0/+6
* clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2022-05-051-1/+9
* clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-051-1/+7
* clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2022-05-051-0/+125
* clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2022-05-051-0/+93
* clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2022-05-051-0/+212
* clk: renesas: Add support for RZ/G2UL SoCBiju Das2022-04-131-0/+6
* clk: renesas: rzg2l: Simplify multiplication/shift logicGeert Uytterhoeven2022-04-131-1/+1
* clk: renesas: rzg2l: Remove unused notifiersPhil Edworthy2022-04-041-2/+0
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-101-0/+6
* clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar2021-11-191-2/+1
* clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar2021-11-191-1/+13
* clk: renesas: rzg2l: Add missing kerneldoc for resetsGeert Uytterhoeven2021-11-151-0/+1
* clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das2021-10-081-0/+118
* clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das2021-09-241-0/+71
* clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das2021-09-241-0/+23
* clk: renesas: rzg2l: Fix clk status functionBiju Das2021-09-241-1/+1
* clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven2021-07-191-0/+750
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