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path: root/drivers/clk/renesas
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* clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1Claudiu Beznea2023-12-131-0/+10
* clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea2023-12-131-15/+44
* clk: renesas: r9a08g045: Add IA55 pclk and its resetClaudiu Beznea2023-12-131-0/+3
* clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()Claudiu Beznea2023-11-271-23/+15
* clk: renesas: r8a779g0: Add PCIe clocksYoshihiro Shimoda2023-11-201-0/+2
* clk: renesas: r8a779g0: Add EtherTSN clockNiklas Söderlund2023-11-201-0/+1
* clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2Claudiu Beznea2023-10-121-0/+34
* clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea2023-10-121-1/+1
* clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea2023-10-105-1/+228
* clk: renesas: rzg2l: Add divider clock for RZ/G3SClaudiu Beznea2023-10-102-0/+197
* clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea2023-10-104-51/+139
* clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic headerClaudiu Beznea2023-10-053-4/+14
* clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea2023-10-051-18/+34
* clk: renesas: rzg2l: Add support for RZ/G3S PLLClaudiu Beznea2023-10-052-4/+48
* clk: renesas: rzg2l: Remove critical areaClaudiu Beznea2023-10-051-4/+1
* clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea2023-10-051-6/+6
* clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea2023-10-051-7/+1
* clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea2023-10-052-11/+14
* clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea2023-10-051-7/+10
* clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme2023-10-051-1/+14
* clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut2023-09-261-2/+2
* clk: renesas: r9a06g032: Name anonymous structsRalph Siemsen2023-09-181-30/+33
* clk: renesas: r9a06g032: Fix kerneldoc warningRalph Siemsen2023-09-181-0/+1
* clk: renesas: rzg2l: Use u32 for flag and mux_flagsClaudiu Beznea2023-09-181-2/+2
* clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea2023-09-181-5/+5
* clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea2023-09-181-3/+2
* clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea2023-09-181-1/+1
* clk: renesas: r9a06g032: Use for_each_compatible_node()Yang Yingliang2023-09-111-3/+2
*-. Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...Stephen Boyd2023-08-3017-19/+73
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| | * clk: Explicitly include correct DT includesRob Herring2023-07-193-4/+1
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| * clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto2023-08-159-1/+9
| * clk: renesas: r8a77965: Add 3DGE and ZG supportGeert Uytterhoeven2023-07-271-0/+2
| * clk: renesas: r8a7796: Add 3DGE and ZG supportGeert Uytterhoeven2023-07-271-0/+2
| * clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven2023-07-271-0/+2
| * clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven2023-07-271-3/+0
| * clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das2023-07-251-0/+3
| * clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET2023-07-111-7/+1
| * clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro2023-07-101-0/+15
| * clk: renesas: r8a774b1: Add 3DGE and ZG supportAdam Ford2023-07-101-0/+2
| * clk: renesas: r8a774e1: Add 3DGE and ZG supportAdam Ford2023-07-101-0/+2
| * clk: renesas: r8a774a1: Add 3DGE and ZG supportAdam Ford2023-07-101-0/+2
| * clk: renesas: rcar-gen3: Add support for ZG clockAdam Ford2023-07-102-4/+32
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*-. Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...Stephen Boyd2023-06-266-49/+27
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| | * clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
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| * clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-11/+5
| * clk: renesas: mstp: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-11/+7
| * clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-20/+11
| * clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das2023-05-232-7/+2
| * clk: renesas: r8a779a0: Add PWM clockWolfram Sang2023-05-081-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2023-04-297-204/+591
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