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linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree
Greg Kroah-Hartman
summary
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commit
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author
committer
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path:
root
/
drivers
/
clk
/
renesas
Commit message (
Expand
)
Author
Age
Files
Lines
*
clk: renesas: r9a07g044: Add GPU clock and reset entries
Biju Das
2021-12-08
1
-0
/
+9
*
clk: renesas: r9a07g044: Add mux and divider for G clock
Biju Das
2021-12-08
2
-0
/
+10
*
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
Biju Das
2021-12-08
1
-2
/
+2
*
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Yoshihiro Shimoda
2021-12-08
5
-0
/
+196
*
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
Yoshihiro Shimoda
2021-12-08
7
-341
/
+437
*
clk: renesas: r9a07g044: Add TSU clock and reset entry
Biju Das
2021-11-26
1
-0
/
+3
*
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
Lad Prabhakar
2021-11-19
1
-2
/
+1
*
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
Lad Prabhakar
2021-11-19
1
-1
/
+14
*
clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
Lad Prabhakar
2021-11-19
1
-2
/
+1
*
clk: renesas: rzg2l: Check return value of pm_genpd_init()
Lad Prabhakar
2021-11-19
1
-1
/
+13
*
clk: renesas: r9a07g044: Add RSPI clock and reset entries
Lad Prabhakar
2021-11-19
1
-0
/
+9
*
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
Biju Das
2021-11-19
1
-1
/
+10
*
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
Biju Das
2021-11-19
1
-0
/
+2
*
clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
Wolfram Sang
2021-11-19
1
-12
/
+3
*
clk: renesas: rcar-gen3: Switch to new SD clock handling
Wolfram Sang
2021-11-19
4
-202
/
+32
*
clk: renesas: r8a779a0: Add SDnH clock to V3U
Wolfram Sang
2021-11-19
1
-1
/
+10
*
clk: renesas: rcar-gen3: Add SDnH clock
Wolfram Sang
2021-11-19
10
-32
/
+64
*
clk: renesas: rcar-gen3: Add dummy SDnH clock
Wolfram Sang
2021-11-19
4
-0
/
+21
*
clk: renesas: r9a07g044: Add OSTM clock and reset entries
Biju Das
2021-11-15
1
-0
/
+9
*
clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
Biju Das
2021-11-15
1
-6
/
+6
*
clk: renesas: r9a07g044: Add WDT clock and reset entries
Biju Das
2021-11-15
1
-0
/
+15
*
clk: renesas: r9a07g044: Add clock and reset entry for SCI1
Lad Prabhakar
2021-11-15
1
-0
/
+3
*
clk: renesas: rzg2l: Add missing kerneldoc for resets
Geert Uytterhoeven
2021-11-15
2
-0
/
+4
*
clk: renesas: r8a779[56]x: Add MLP clocks
Andrey Gusakov
2021-10-15
3
-0
/
+3
*
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Biju Das
2021-10-08
2
-0
/
+40
*
clk: renesas: rzg2l: Add SDHI clk mux support
Biju Das
2021-10-08
2
-0
/
+130
*
clk: renesas: r8a779a0: Add RPC support
Wolfram Sang
2021-10-08
1
-0
/
+32
*
clk: renesas: cpg-lib: Move RPC clock registration to the library
Wolfram Sang
2021-10-08
3
-87
/
+92
*
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...
Lad Prabhakar
2021-10-08
2
-0
/
+21
*
clk: renesas: r8a779a0: Add Z0 and Z1 clock support
Geert Uytterhoeven
2021-09-28
1
-0
/
+158
*
clk: renesas: r9a07g044: Add GbEthernet clock/reset
Biju Das
2021-09-24
1
-0
/
+10
*
clk: renesas: rzg2l: Add support to handle coupled clocks
Biju Das
2021-09-24
2
-1
/
+81
*
clk: renesas: r9a07g044: Add ethernet clock sources
Biju Das
2021-09-24
2
-1
/
+21
*
clk: renesas: rzg2l: Add support to handle MUX clocks
Biju Das
2021-09-24
2
-0
/
+35
*
clk: renesas: r8a779a0: Add TPU clock
Wolfram Sang
2021-09-24
1
-0
/
+1
*
clk: renesas: rzg2l: Fix clk status function
Biju Das
2021-09-24
1
-1
/
+1
*
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
Biju Das
2021-09-24
1
-0
/
+2
*
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
2021-09-02
10
-26
/
+87
|
\
|
*
clk: renesas: Make CLK_R9A06G032 invisible
Geert Uytterhoeven
2021-08-13
1
-3
/
+1
|
*
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
Lad Prabhakar
2021-07-26
1
-1
/
+2
|
*
clk: renesas: r9a07g044: Add clock and reset entries for ADC
Lad Prabhakar
2021-07-19
1
-0
/
+6
|
*
clk: renesas: r9a07g044: Add clock and reset entries for CANFD
Lad Prabhakar
2021-07-19
1
-0
/
+4
|
*
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
Geert Uytterhoeven
2021-07-19
4
-3
/
+3
|
*
clk: renesas: r9a07g044: Add GPIO clock and reset entries
Lad Prabhakar
2021-07-19
1
-0
/
+5
|
*
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
Biju Das
2021-07-19
1
-0
/
+20
|
*
clk: renesas: r9a07g044: Add USB clocks/resets
Biju Das
2021-07-19
1
-0
/
+12
|
*
clk: renesas: r9a07g044: Add DMAC clocks/resets
Biju Das
2021-07-19
1
-0
/
+8
|
*
clk: renesas: r9a07g044: Add I2C clocks/resets
Biju Das
2021-07-19
1
-0
/
+12
|
*
clk: renesas: r8a779a0: Add the DSI clocks
Kieran Bingham
2021-07-19
1
-1
/
+3
|
*
clk: renesas: r8a779a0: Add the DU clock
Kieran Bingham
2021-07-19
1
-0
/
+1
[next]