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path: root/drivers/clk/renesas
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* clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov2021-10-153-0/+3
* clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das2021-10-082-0/+40
* clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das2021-10-082-0/+130
* clk: renesas: r8a779a0: Add RPC supportWolfram Sang2021-10-081-0/+32
* clk: renesas: cpg-lib: Move RPC clock registration to the libraryWolfram Sang2021-10-083-87/+92
* clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar2021-10-082-0/+21
* clk: renesas: r8a779a0: Add Z0 and Z1 clock supportGeert Uytterhoeven2021-09-281-0/+158
* clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das2021-09-241-0/+10
* clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das2021-09-242-1/+81
* clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das2021-09-242-1/+21
* clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das2021-09-242-0/+35
* clk: renesas: r8a779a0: Add TPU clockWolfram Sang2021-09-241-0/+1
* clk: renesas: rzg2l: Fix clk status functionBiju Das2021-09-241-1/+1
* clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das2021-09-241-0/+2
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2021-09-0210-26/+87
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| * clk: renesas: Make CLK_R9A06G032 invisibleGeert Uytterhoeven2021-08-131-3/+1
| * clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar2021-07-261-1/+2
| * clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar2021-07-191-0/+6
| * clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar2021-07-191-0/+4
| * clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven2021-07-194-3/+3
| * clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar2021-07-191-0/+5
| * clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das2021-07-191-0/+20
| * clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das2021-07-191-0/+12
| * clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das2021-07-191-0/+8
| * clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das2021-07-191-0/+12
| * clk: renesas: r8a779a0: Add the DSI clocksKieran Bingham2021-07-191-1/+3
| * clk: renesas: r8a779a0: Add the DU clockKieran Bingham2021-07-191-0/+1
| * clk: renesas: rzg2: Rename i2c-dvfs to iic-pmicGeert Uytterhoeven2021-07-194-4/+4
| * clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()Lad Prabhakar2021-07-191-1/+1
| * clk: renesas: rzg2l: Avoid mixing error pointers and NULLDan Carpenter2021-07-191-1/+1
| * clk: renesas: rzg2l: Fix a double free on errorDan Carpenter2021-07-191-7/+1
| * clk: renesas: rzg2l: Fix return value and unused assignmentYang Li2021-07-191-4/+2
| * clk: renesas: rzg2l: Remove unneeded semicolonYang Li2021-07-191-1/+1
* | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2021-08-291-1/+1
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| * clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereferenceAdam Ford2021-08-281-1/+1
* | dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das2021-07-123-64/+93
* | clk: renesas: r9a07g044: Add P2 Clock supportBiju Das2021-07-122-0/+5
* | clk: renesas: r9a07g044: Fix P1 ClockBiju Das2021-07-121-3/+3
* | clk: renesas: r9a07g044: Rename divider tableBiju Das2021-07-121-3/+4
* | clk: renesas: rzg2l: Add multi clock PM supportBiju Das2021-07-121-22/+29
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* clk: renesas: Add support for R9A07G044 SoCLad Prabhakar2021-06-105-0/+141
* clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar2021-06-104-0/+883
* clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto2021-05-271-0/+1
* clk: renesas: cpg-mssr: Make srstclr[] comment block consistentGeert Uytterhoeven2021-05-271-1/+3
* clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitionsGeert Uytterhoeven2021-05-271-6/+0
* clk: renesas: r9a06g032: Switch to .determine_rate()Geert Uytterhoeven2021-05-111-12/+13
* clk: renesas: div6: Implement range checkingGeert Uytterhoeven2021-05-111-1/+7
* clk: renesas: div6: Consider all parents for requested rateGeert Uytterhoeven2021-05-111-3/+32
* clk: renesas: div6: Switch to .determine_rate()Geert Uytterhoeven2021-05-111-5/+7
* clk: renesas: div6: Simplify src mask handlingGeert Uytterhoeven2021-05-111-20/+11
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 12:38:32 +0000