| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name | Alex Bee | 2023-11-28 | 1 | -1/+1 |
| * | clk: rockchip: rk3128: Fix aclk_peri_src's parent | Finley Xiao | 2023-11-28 | 1 | -13/+7 |
| * | clk: rockchip: rk3128: Fix HCLK_OTG gate register | Weihao Li | 2023-11-16 | 1 | -1/+1 |
| * | clk: rockchip: support more core div setting | Elaine Zhang | 2021-03-21 | 1 | -3/+4 |
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 2019-05-30 | 1 | -10/+1 |
| * | clk: Remove io.h from clk-provider.h | Stephen Boyd | 2019-05-15 | 1 | -0/+1 |
| * | clk: rockchip: add sclk_timer5 as critical clock on rk3128 | Elaine Zhang | 2017-09-17 | 1 | -0/+1 |
| * | clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error | Elaine Zhang | 2017-09-17 | 1 | -4/+4 |
| * | clk: rockchip: add pclk_pmu as critical clock on rk3128 | Elaine Zhang | 2017-09-17 | 1 | -1/+2 |
| * | clk: rockchip: modify rk3128 clk driver to also support rk3126 | Elaine Zhang | 2017-08-08 | 1 | -14/+55 |
| * | clk: rockchip: add clock controller for rk3128 | Elaine Zhang | 2017-06-02 | 1 | -0/+612 |
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