| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk/rockchip: Use of_device_get_match_data() | Minghao Chi (CGEL ZTE) | 2022-02-23 | 1 | -4/+2 |
| * | clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 | Sascha Hauer | 2022-02-08 | 1 | -1/+1 |
| * | clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 | Sascha Hauer | 2022-02-08 | 1 | -3/+3 |
| * | clk: rockchip: Add more PLL rates for rk3568 | Sascha Hauer | 2022-02-08 | 1 | -0/+6 |
| * | clk: rockchip: drop module parts from rk3399 and rk3568 drivers | Heiko Stuebner | 2021-11-02 | 1 | -4/+0 |
| * | Revert "clk: rockchip: use module_platform_driver_probe" | Heiko Stuebner | 2021-11-02 | 1 | -1/+1 |
| * | clk: rockchip: use module_platform_driver_probe | Miles Chen | 2021-09-21 | 1 | -1/+1 |
| * | clk: rockchip: fix rk3568 cpll clk gate bits | Peter Geis | 2021-05-24 | 1 | -5/+5 |
| * | clk: rockchip: add clock controller for rk3568 | Elaine Zhang | 2021-03-21 | 1 | -0/+1725 |
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