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path: root/drivers/clk/rockchip
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* clk: rockchip: fix error for unknown clocksSebastian Reichel2024-10-101-1/+2
* clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_pAlexander Shiyan2024-10-041-1/+1
* clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228Jonas Karlman2024-10-041-1/+1
* clk: rockchip: rk3568: Add PLL rate for 724 MHzLucas Stach2024-05-041-0/+1
* clk: rockchip: Remove an unused field in struct rockchip_mmc_clockChristophe JAILLET2024-05-041-1/+0
* clk: rockchip: rk3588: Add reset line for HDMI ReceiverShreeya Patel2024-04-101-0/+1
* clk: rockchip: rk3568: Add missing USB480M_PHY muxDavid Jander2024-04-101-0/+4
* clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parentOndrej Jirman2024-02-271-3/+3
* clk: rockchip: rk3588: use linked clock ID for GATE_LINKSebastian Reichel2024-02-271-23/+23
* clk: rockchip: rk3588: fix indentSebastian Reichel2024-02-271-1/+1
* clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grfSebastian Reichel2024-02-271-6/+4
* Merge branch 'v6.9-shared/clkids' into v6.9-clk/nextHeiko Stuebner2024-02-273-1/+23
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| * clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel2024-02-273-1/+23
* | clk: rockchip: rk3568: Add PLL rate for 128MHzChris Morgan2024-01-251-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2024-01-121-0/+3
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| * clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan2023-12-051-0/+1
| * clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan2023-12-051-0/+1
| * clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan2023-11-161-0/+1
* | clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee2023-11-281-1/+1
* | clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao2023-11-281-13/+7
* | clk: rockchip: rk3128: Fix HCLK_OTG gate registerWeihao Li2023-11-161-1/+1
* | clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan2023-11-161-0/+1
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* clk: Use device_get_match_data()Rob Herring2023-10-231-7/+2
*-. Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2023-08-302-1/+61
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| | * clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki2023-08-101-0/+59
| | * clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHzAlibek Omarov2023-07-101-1/+1
| | * clk: rockchip: rk3568: Add PLL rate for 101MHzAlibek Omarov2023-07-101-0/+1
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* / clk: Explicitly include correct DT includesRob Herring2023-07-192-2/+2
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*-. Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into cl...Stephen Boyd2023-04-252-17/+27
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| | * clk: rockchip: rk3588: make gate linked clocks criticalSebastian Reichel2023-04-181-16/+26
| | * clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparentQuentin Schulz2023-03-071-1/+1
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* / clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_div...Christophe JAILLET2023-04-051-2/+0
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*-. Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into cl...Stephen Boyd2022-12-129-35/+3795
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| | * clk: rockchip: Fix memory leak in rockchip_clk_register_pll()Xiu Jianfeng2022-11-231-0/+1
| | * clk: rockchip: add clock controller for the RK3588Elaine Zhang2022-11-155-1/+3447
| | * clk: rockchip: add lookup table supportSebastian Reichel2022-11-142-15/+40
| | * clk: rockchip: simplify rockchip_clk_add_lookupSebastian Reichel2022-11-142-10/+6
| | * clk: rockchip: allow additional mux options for cpu-clock frequency changesElaine Zhang2022-11-142-0/+43
| | * clk: rockchip: add pll type for RK3588Elaine Zhang2022-11-142-1/+235
| | * clk: rockchip: add register offset of the cores select parentElaine Zhang2022-11-142-8/+23
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* / clk: Remove a useless includeChristophe JAILLET2022-11-221-1/+0
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* clk: rockchip: Add clock controller support for RV1126 SoCJagan Teki2022-09-234-0/+1165
* clk: rockchip: Add MUXTBL variantElaine Zhang2022-09-132-6/+38
* clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer2022-05-031-0/+1
* clk: rockchip: re-add rational best approximation algorithm to the fractional...Quentin Schulz2022-02-241-0/+3
* clk/rockchip: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)2022-02-231-4/+2
* clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568Sascha Hauer2022-02-081-1/+1
* clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568Sascha Hauer2022-02-081-3/+3
* clk: rockchip: Add more PLL rates for rk3568Sascha Hauer2022-02-081-0/+6
* clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner2021-11-023-10/+2
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 18:17:45 +0000